/branches/arm/boot/arch/arm32/loader/mm.h |
---|
1,5 → 1,5 |
/* |
* Copyright (c) 2003-2004 Jakub Jermar |
* Copyright (c) 2007 Pavel Jancik, Michal Kebrt |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
26,7 → 26,7 |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup arm32mm |
/** @addtogroup arm32boot |
* @{ |
*/ |
/** @file |
36,7 → 36,9 |
#ifndef __MM_H__ |
#define __MM_H__ |
#ifndef __ASM__ |
#include "types.h" |
#endif |
#define FRAME_WIDTH 12 /* 4KB frames */ |
53,27 → 55,28 |
# define PA2KA(x) ((x) + 0x80000000) |
#endif |
#define PTL0_ENTRIES_ARCH (2<<12) /* 4096 */ |
#define SET_PTL0_ADDRESS_ARCH(ptl0) ( set_ptl0_addr((pte_level0_section *)(ptl0)) ) |
/** Number of entries in PTL0 */ |
#define PTL0_ENTRIES_ARCH (2<<12) /* 4096 */ |
/** Frames per 1MB section */ |
#define FRAMES_PER_SECTION ( ( 1 << 20 ) / FRAME_SIZE ) |
/** Converts adress to frame */ |
/** Converts adress to frame number */ |
#define ADDR2PFN( addr ) ( ((uintptr_t)(addr))>>FRAME_WIDTH ) |
/** Value of descriptor_type in page table entry that signals |
* that this entry describe section |
*/ |
/** Descriptor type that signs "section" page table entry |
* (one-level paging with 1MB sized pages) */ |
#define PTE_DESCRIPTOR_SECTION 2 |
/** Rights: user-no acess, kernel-read/write */ |
/** Access rights to page table: user-no access, kernel-read/write */ |
#define PTE_AP_USER_NO_KERNEL_RW 1 |
#ifndef __ASM__ |
/** Page table level 0 entry - section format */ |
/** Page table level 0 entry - "section" format (one-level paging, 1MB sized |
* pages). Used only for booting the kernel. */ |
typedef struct { |
unsigned descriptor_type : 2; // should be 2 |
unsigned descriptor_type : 2; // PTE_DESCRIPTOR_SECTION |
unsigned bufferable : 1; |
unsigned cacheable : 1; |
unsigned machine_depend : 1; |
85,10 → 88,10 |
} __attribute__ ((packed)) pte_level0_section; |
/** Set adress of paging level 0 table |
* \param pt pointer to page table to set |
/** Sets the address of level 0 page table. |
* \param pt pointer to the page table to set |
*/ |
static inline void set_ptl0_addr( pte_level0_section* pt) { |
static inline void set_ptl0_address( pte_level0_section* pt) { |
asm volatile ( "mcr p15, 0, %0, c2, c0, 0 \n" |
: |
: "r"(pt) |
96,11 → 99,13 |
} |
/** Page table that holds 1:1 mapping for kernel starting */ |
/** Page table that holds 1:1 mapping for booting the kernel. */ |
extern pte_level0_section page_table[PTL0_ENTRIES_ARCH]; |
/** Sets memory mapping for kernel */ |
void mm_kernel_mapping(void); |
#endif |
#endif |
/branches/arm/boot/arch/arm32/loader/boot.S |
---|
27,10 → 27,13 |
# |
#include "mm.h" |
.section BOOTSTRAP |
.global start |
.global jump_to_kernel |
.global page_table |
start: |
b bootstrap |
39,9 → 42,9 |
bx r0 |
# align for start of page |
.section PT |
# align for start of page |
.global page_table |
# make place for first level page table |
page_table: |
.skip 4096*4 |
# make place for first level page table |
.skip PTL0_ENTRIES_ARCH * 4 |
/branches/arm/boot/arch/arm32/loader/main.c |
---|
74,8 → 74,6 |
components[i].start, components[i].name, components[i].size); |
} |
printf("\nAddr of page table : %L\n", page_table); |
printf("\nCopying components\n"); |
unsigned int top = 0; |
bootinfo.cnt = 0; |
82,7 → 80,6 |
for (i = 0; i < COMPONENTS; i++) { |
printf(" %s...", components[i].name); |
top = ALIGN_UP(top, PAGE_SIZE); |
//printf("top %x", KERNEL_PHY_ADDRESS + top); |
memcpy(((void *) KERNEL_PHY_ADDRESS) + top, components[i].start, components[i].size); |
if (i > 0) { |
bootinfo.tasks[bootinfo.cnt].addr = ((void *) KERNEL_PHY_ADDRESS) + top; |
90,17 → 87,6 |
bootinfo.cnt++; |
} |
/* TODO: memcpy test -> to be deleted */ |
/* |
unsigned char x, y; |
for (j=0; j < 20; ++j) { |
x = *((unsigned char *) components[i].start + j); |
y = *((unsigned char *) KERNEL_PHY_ADDRESS + top + j); |
if (x != y) { |
printf("!!! Error, %x != %x\n", x,y); |
} |
} |
*/ |
top += components[i].size; |
printf("done.\n"); |
} |
/branches/arm/boot/arch/arm32/loader/mm.c |
---|
1,5 → 1,5 |
/* |
* Copyright (c) 2003-2004 Jakub Jermar |
* Copyright (c) 2007 Pavel Jancik, Michal Kebrt |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
26,20 → 26,24 |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup arm32mm |
/** @addtogroup arm32boot |
* @{ |
*/ |
/** @file |
*/ |
#include "mm.h" |
/** Set page table entry to point no frame, be read/write by kernel, |
* no access by user, become to domain 0, no cache or buffer |
* \param pte page table entry to set |
* \param frame frame number of first frame 1MB section |
* Note: If frame not aligned it's used first lower 1MB aligned frame |
/** Initializes section page table entry. |
* |
* Will be readable/writable by kernel with no access from user mode. |
* Will belong to domain 0. No cache or buffering is enabled. |
* |
* \param pte page table entry to set |
* \param frame first frame in the section (frame number) |
* \note If frame is not 1MB aligned, first lower 1MB aligned frame will be used. |
*/ |
static void init_pte_level0_section_entry( pte_level0_section* pte, unsigned frame){ |
static void init_pte_level0_section(pte_level0_section* pte, unsigned frame){ |
pte->descriptor_type = PTE_DESCRIPTOR_SECTION; |
pte->bufferable = 0; // disable |
pte->cacheable = 0; |
54,32 → 58,33 |
void mm_kernel_mapping(void) { |
int i; |
// Create 1:1 mapping |
for( i=0; i < PTL0_ENTRIES_ARCH; i++) { |
init_pte_level0_section_entry(&page_table[i], i * FRAMES_PER_SECTION); |
const unsigned int first_kernel_section = ADDR2PFN(PA2KA(0)) / FRAMES_PER_SECTION; |
// create 1:1 mapping (in lower 2GB) |
for(i = 0; i < first_kernel_section; i++) { |
init_pte_level0_section(&page_table[i], i * FRAMES_PER_SECTION); |
} |
// Create kernel mapping |
const unsigned int offset = ADDR2PFN(PA2KA(0)) / FRAMES_PER_SECTION; |
for( i = offset; i < PTL0_ENTRIES_ARCH; i++) { |
init_pte_level0_section_entry(&page_table[i], (i - offset) * FRAMES_PER_SECTION); |
// create kernel mapping (in upper 2GB), physical addresses starting from 0 |
for(i = first_kernel_section; i < PTL0_ENTRIES_ARCH; i++) { |
init_pte_level0_section(&page_table[i], (i - first_kernel_section) * FRAMES_PER_SECTION); |
} |
SET_PTL0_ADDRESS_ARCH( page_table); |
set_ptl0_address(page_table); |
// Enable paging |
// enable paging |
asm volatile ( |
"ldr r0, =0x55555555 \n" |
"mcr p15, 0, r0, c3, c0, 0 \n" // Set domain acces rights to client <==> take rights from page tables |
"mrc p15, 0, r0, c1, c0, 0 \n" // Get current setting of system ... register 1 isn't only for memmory management |
"ldr r1, =0xFFFFFE8D \n" // Mask to disable aligment checks; system & rom bit disable |
"and r0, r0, r1 \n" |
"ldr r1, =0x00000001 \n" // Mask to enable paging |
"orr r0, r0, r1 \n" |
"mcr p15, 0, r0, c1, c0, 0 \n" // Store setting |
: |
: |
: "r0", "r1" |
"ldr r0, =0x55555555 \n" |
"mcr p15, 0, r0, c3, c0, 0 \n" // TODO: comment: set domain access rights to client <==> take rights from page tables |
"mrc p15, 0, r0, c1, c0, 0 \n" // get current settings of system |
"ldr r1, =0xFFFFFE8D \n" // mask to disable aligment checks; system & rom bit disabled |
"and r0, r0, r1 \n" |
"ldr r1, =0x00000001 \n" // mask to enable paging |
"orr r0, r0, r1 \n" |
"mcr p15, 0, r0, c1, c0, 0 \n" // store settings |
: |
: |
: "r0", "r1" |
); |
}; |