/boot/trunk/arch/ppc32/loader/spr.h |
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File deleted |
/boot/trunk/arch/ppc32/loader/asm.S |
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27,7 → 27,6 |
# |
#include "regname.h" |
#include "spr.h" |
.data |
164,18 → 163,18 |
# Invalidate instruction cache |
li r3, 0 |
ori r3, r3, (HID0_ICE | HID0_DCE | HID0_ICFI | HID0_DCI) |
mfspr r4, SPRN_HID0 |
ori r3, r3, (hid0_ice | hid0_dce | hid0_icfi | hid0_dci) |
mfspr r4, hid0 |
or r5, r4, r3 |
isync |
mtspr SPRN_HID0, r5 |
mtspr hid0, r5 |
sync |
isync |
# Enable instruction cache |
ori r5, r4, HID0_ICE |
mtspr SPRN_HID0, r5 |
ori r5, r4, hid0_ice |
mtspr hid0, r5 |
sync |
isync |
blr |
184,4 → 183,3 |
mr r10, r4 |
mtlr r3 |
blr |
/boot/trunk/arch/ppc32/loader/regname.h |
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26,8 → 26,8 |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
#ifndef __REGNAME_H__ |
#define __REGNAME_H__ |
#ifndef __ppc32_REGNAME_H__ |
#define __ppc32_REGNAME_H__ |
/* Condition Register Bit Fields */ |
#define cr0 0 |
188,5 → 188,20 |
#define sprg2 274 |
#define sprg3 275 |
#define prv 287 |
#define hid0 1008 |
/* MSR bits */ |
#define msr_ir (1 << 4) |
#define msr_dr (1 << 5) |
/* HID0 bits */ |
#define hid0_ice (1 << 15) |
#define hid0_dce (1 << 14) |
#define hid0_icfi (1 << 11) |
#define hid0_dci (1 << 10) |
/* Cache sizes */ |
#define L1_CACHE_LINES (128 * 8) |
#define L1_CACHE_BYTES 5 |
#endif |