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Ignore whitespace Rev 250 → Rev 251

/SPARTAN/trunk/include/cpu.h
74,7 → 74,6
extern cpu_t *cpus;
 
extern void cpu_init(void);
extern void cpu_halt(void);
 
extern void cpu_arch_init(void);
extern void cpu_identify(void);
/SPARTAN/trunk/src/mm/page.c
83,7 → 83,7
newpt = frame_alloc(FRAME_KA);
memsetb(newpt, PAGE_SIZE, 0);
SET_PTL1_ADDRESS(ptl0, PTL0_INDEX(page), KA2PA(newpt));
SET_PTL1_FLAGS(ptl0, PTL0_INDEX(page), PAGE_PRESENT | PAGE_USER);
SET_PTL1_FLAGS(ptl0, PTL0_INDEX(page), PAGE_PRESENT | PAGE_USER | PAGE_EXEC);
}
 
ptl1 = (pte_t *) PA2KA(GET_PTL1_ADDRESS(ptl0, PTL0_INDEX(page)));
92,7 → 92,7
newpt = frame_alloc(FRAME_KA);
memsetb(newpt, PAGE_SIZE, 0);
SET_PTL2_ADDRESS(ptl1, PTL1_INDEX(page), KA2PA(newpt));
SET_PTL2_FLAGS(ptl1, PTL1_INDEX(page), PAGE_PRESENT | PAGE_USER);
SET_PTL2_FLAGS(ptl1, PTL1_INDEX(page), PAGE_PRESENT | PAGE_USER | PAGE_EXEC);
}
 
ptl2 = (pte_t *) PA2KA(GET_PTL2_ADDRESS(ptl1, PTL1_INDEX(page)));
101,7 → 101,7
newpt = frame_alloc(FRAME_KA);
memsetb(newpt, PAGE_SIZE, 0);
SET_PTL3_ADDRESS(ptl2, PTL2_INDEX(page), KA2PA(newpt));
SET_PTL3_FLAGS(ptl2, PTL2_INDEX(page), PAGE_PRESENT | PAGE_USER);
SET_PTL3_FLAGS(ptl2, PTL2_INDEX(page), PAGE_PRESENT | PAGE_USER | PAGE_EXEC);
}
 
ptl3 = (pte_t *) PA2KA(GET_PTL3_ADDRESS(ptl2, PTL2_INDEX(page)));
/SPARTAN/trunk/arch/amd64/include/cpuid.h
31,6 → 31,9
 
#include <arch/types.h>
 
#define AMD_CPUID_EXTENDED 0x80000001
#define AMD_EXT_NOEXECUTE 20
 
struct cpu_info {
__u32 cpuid_eax;
__u32 cpuid_ebx;
40,21 → 43,9
 
extern int has_cpuid(void);
 
static inline void cpuid(__u32 cmd, cpu_info_t *info)
{
__asm__ (
"movl %1, %eax"
"cpuid"
"movl %eax, 0(%0)"
"movl %ebx, 4(%0)"
"movl %ecx, 8(%0)"
"movl %edx, 12(%0)"
: "=m"(info)
: "r"(cmd)
: "%eax","%ebx","%ecx","%edx"
);
}
extern void cpuid(__u32 cmd, cpu_info_t *info);
 
 
extern __u64 rdtsc(void);
 
#endif
/SPARTAN/trunk/arch/amd64/include/mm/page.h
42,7 → 42,7
# define PA2KA(x) (((__address) (x)) - 0x80000000)
#else
# define KA2PA(x) ((x) + 0x80000000)
//# define PA2KA(x) ((x)) - 0x80000000)
# define PA2KA(x) ((x) - 0x80000000)
#endif
 
#define PTL0_INDEX_ARCH(vaddr) (((vaddr)>>39)&0x1ff)
/SPARTAN/trunk/arch/amd64/include/cpu.h
29,11 → 29,18
#ifndef __amd64_CPU_H__
#define __amd64_CPU_H__
 
#include <config.h>
#include <proc/thread.h>
 
#define EFER_MSR_NUM 0xc0000080
#define AMD_SCE_FLAG 0
#define AMD_LME_FLAG 8
#define AMD_LMA_FLAG 10
#define AMD_FFXSR_FLAG 14
#define AMD_NXE_FLAG 11
 
#ifndef __ASM__
 
#include <typedefs.h>
#include <arch/pm.h>
#include <arch/asm.h>
 
struct cpu_arch {
int vendor;
44,7 → 51,11
};
 
 
void set_TS_flag(void);
void reset_TS_flag(void);
extern void set_TS_flag(void);
extern void reset_TS_flag(void);
extern void set_efer_flag(int flag);
extern __u64 read_efer_flag(void);
 
#endif /* __ASM__ */
 
#endif
/SPARTAN/trunk/arch/amd64/Makefile.inc
33,4 → 33,5
arch/mm/tlb.c \
arch/asm_utils.S \
arch/fmath.c \
arch/mm/memory_init.c
arch/mm/memory_init.c \
arch/cpu/cpu.c
/SPARTAN/trunk/arch/amd64/src/asm_utils.S
39,6 → 39,7
.text
.global interrupt_handlers
.global panic_printf
.global cpuid
 
panic_printf:
movq $halt, (%rsp)
46,8 → 47,9
 
.global has_cpuid
.global rdtsc
 
 
.global read_efer_flag
.global set_efer_flag
## Determine CPUID support
#
# Return 0 in EAX if CPUID is not support, 1 if supported.
70,12 → 72,36
popq %rbx
ret
 
cpuid:
movq %rbx, %r10 # we have to preserve rbx across function calls
 
movl %edi,%eax # load the command into %eax
 
cpuid
movl %eax,0(%rsi)
movl %ebx,4(%rsi)
movl %ecx,8(%rsi)
movl %edx,12(%rsi)
 
movq %r10, %rbx
ret
 
rdtsc:
xorq %rax,%rax
rdtsc
ret
 
set_efer_flag:
movq $0xc0000080, %rcx
rdmsr
btsl %edi, %eax
wrmsr
ret
read_efer_flag:
movq $0xc0000080, %rcx
rdmsr
ret
 
# Push all general purpose registers on stack except %rbp, %rsp
.macro push_all_gpr
/SPARTAN/trunk/arch/amd64/src/boot/boot.S
31,6 → 31,7
#include <arch/mm/page.h>
#include <arch/mm/ptl.h>
#include <arch/pm.h>
#include <arch/cpu.h>
 
#define START_STACK 0x7c00
#define START_STACK_64 0xffffffff80007c00
101,9 → 102,9
movl %eax, %cr3
# Enable long mode
movl $0xc0000080, %ecx # EFER MSR number
movl $EFER_MSR_NUM, %ecx # EFER MSR number
rdmsr # Read EFER
btsl $8, %eax # Set LME=1
btsl $AMD_LME_FLAG, %eax # Set LME=1
wrmsr # Write EFER
# Enable paging to activate long mode (set CR0.PG=1)
/SPARTAN/trunk/arch/amd64/src/cpu/cpu.c
0,0 → 1,87
/*
* Copyright (C) 2001-2004 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
 
#include <arch/cpu.h>
#include <arch/cpuid.h>
#include <arch/pm.h>
 
#include <arch.h>
#include <arch/types.h>
#include <print.h>
#include <typedefs.h>
 
/*
* Identification of CPUs.
* Contains only non-MP-Specification specific SMP code.
*/
#define AMD_CPUID_EBX 0x68747541
#define AMD_CPUID_ECX 0x444d4163
#define AMD_CPUID_EDX 0x69746e65
 
#define INTEL_CPUID_EBX 0x756e6547
#define INTEL_CPUID_ECX 0x6c65746e
#define INTEL_CPUID_EDX 0x49656e69
 
 
enum vendor {
VendorUnknown=0,
VendorAMD,
VendorIntel
};
 
static char *vendor_str[] = {
"Unknown Vendor",
"AuthenticAMD",
"GenuineIntel"
};
 
void set_TS_flag(void)
{
asm
(
"mov %%cr0,%%rax;"
"or $8,%%rax;"
"mov %%rax,%%cr0;"
:
:
:"%rax"
);
}
 
void reset_TS_flag(void)
{
asm
(
"mov %%cr0,%%rax;"
"btc $4,%%rax;"
"mov %%rax,%%cr0;"
:
:
:"%rax"
);
}
/SPARTAN/trunk/arch/amd64/src/amd64.c
39,9 → 39,22
 
#include <arch/bios/bios.h>
#include <arch/mm/memory_init.h>
#include <arch/cpu.h>
#include <print.h>
#include <arch/cpuid.h>
 
void arch_pre_mm_init(void)
{
struct cpu_info cpuid_s;
 
cpuid(AMD_CPUID_EXTENDED,&cpuid_s);
if (! (cpuid_s.cpuid_edx & (1<<AMD_EXT_NOEXECUTE))) {
printf("We do not support NX!!-----------\n");
printf("%X------\n",cpuid_s.cpuid_edx);
cpu_halt();
}
set_efer_flag(AMD_NXE_FLAG);
 
pm_init();
 
if (config.cpu_active == 1) {
/SPARTAN/trunk/arch/amd64/src/dummy.s
35,7 → 35,6
.global cpu_sleep
.global cpu_print_report
.global dummy
.global reset_TS_flag
.global fpu_init
before_thread_runs_arch:
44,7 → 43,6
cpu_arch_init:
cpu_sleep:
cpu_print_report:
reset_TS_flag:
fpu_init:
dummy: