/SPARTAN/trunk/test/synch/semaphore1/test.c |
---|
42,8 → 42,8 |
static semaphore_t sem; |
static waitq_t can_start; |
static int items_produced; |
static int items_consumed; |
static volatile int items_produced; |
static volatile int items_consumed; |
static void consumer(void *arg); |
static void producer(void *arg); |
/SPARTAN/trunk/test/synch/rwlock5/test.c |
---|
41,8 → 41,8 |
static rwlock_t rwlock; |
static waitq_t can_start; |
static int items_read; |
static int items_written; |
static volatile int items_read; |
static volatile int items_written; |
static void writer(void *arg); |
static void reader(void *arg); |
/SPARTAN/trunk/test/fpu/fpu1/test.c |
---|
69,7 → 69,7 |
panic("tid%d: e*10e8=%d\n", THREAD->tid, (int) 100000000*e); |
} |
atomic_inc((int *) &threads_ok); |
atomic_inc(&threads_ok); |
} |
static void pi(void *data) |
99,7 → 99,7 |
panic("tid%d: pi*10e8=%d\n", THREAD->tid, (int) 100000000*pi); |
} |
atomic_inc((int *) &threads_ok); |
atomic_inc(&threads_ok); |
} |
/SPARTAN/trunk/include/mm/page.h |
---|
46,6 → 46,47 |
#define PAGE_WRITE (1<<4) |
#define PAGE_EXEC (1<<5) |
/* |
* This is the generic 4-level page table interface. |
* Architectures are supposed to implement *_ARCH macros. |
*/ |
/* |
* These macros process vaddr and extract those portions |
* of it that function as indices to respective page tables. |
*/ |
#define PTL0_INDEX(vaddr) PTL0_INDEX_ARCH(vaddr) |
#define PTL1_INDEX(vaddr) PTL1_INDEX_ARCH(vaddr) |
#define PTL2_INDEX(vaddr) PTL2_INDEX_ARCH(vaddr) |
#define PTL3_INDEX(vaddr) PTL3_INDEX_ARCH(vaddr) |
/* |
* These macros traverse the 4-level tree of page tables, |
* each descending by one level. |
*/ |
#define GET_PTL1_ADDRESS(ptl0, i) GET_PTL1_ADDRESS_ARCH(ptl0, i) |
#define GET_PTL2_ADDRESS(ptl1, i) GET_PTL2_ADDRESS_ARCH(ptl1, i) |
#define GET_PTL3_ADDRESS(ptl2, i) GET_PTL3_ADDRESS_ARCH(ptl2, i) |
#define GET_FRAME_ADDRESS(ptl3, i) GET_FRAME_ADDRESS_ARCH(ptl3, i) |
/* |
* These macros are provided to change shape of the 4-level |
* tree of page tables on respective level. |
*/ |
#define SET_PTL1_ADDRESS(ptl0, i, a) SET_PTL1_ADDRESS_ARCH(ptl0, i, a) |
#define SET_PTL2_ADDRESS(ptl1, i, a) SET_PTL2_ADDRESS_ARCH(ptl1, i, a) |
#define SET_PTL3_ADDRESS(ptl2, i, a) SET_PTL3_ADDRESS_ARCH(ptl2, i, a) |
#define SET_FRAME_ADDRESS(ptl3, i, a) SET_FRAME_ADDRESS_ARCH(ptl3, i, a) |
/* |
* These macros are provided to set/clear various flags within the page tables. |
*/ |
#define SET_PTL1_FLAGS(ptl0, i, x) SET_PTL1_FLAGS_ARCH(ptl0, i, x) |
#define SET_PTL2_FLAGS(ptl1, i, x) SET_PTL2_FLAGS_ARCH(ptl1, i, x) |
#define SET_PTL3_FLAGS(ptl2, i, x) SET_PTL3_FLAGS_ARCH(ptl2, i, x) |
#define SET_FRAME_FLAGS(ptl3, i, x) SET_FRAME_FLAGS_ARCH(ptl3, i, x) |
extern void page_init(void); |
extern void map_page_to_frame(__address page, __address frame, int flags, __address root); |
extern void map_structure(__address s, size_t size); |
/SPARTAN/trunk/doc/mm |
---|
0,0 → 1,52 |
Memory management |
================= |
SPARTAN kernel deploys generic interface for 4-level page tables, |
no matter what the real underlying hardware architecture is. |
VADDR |
+-----------------------------------------------------------------------------+ |
| PTL0_INDEX | PTL1_INDEX | PTL2_INDEX | PTL3_INDEX | OFFSET | |
+-----------------------------------------------------------------------------+ |
PTL0 PTL1 PTL2 PTL3 |
+--------+ +--------+ +--------+ +--------+ |
| | | | | PTL3 | -----\ | | |
| | | | +--------+ | | | |
| | +--------+ | | | | | |
| | | PTL2 | -----\ | | | | | |
| | +--------+ | | | | | | |
| | | | | | | | +--------+ |
+--------+ | | | | | | | FRAME | |
| PTL1 | -----\ | | | | | | +--------+ |
+--------+ | | | | | | | | | |
| | | | | | | | | | | |
| | | | | | | | | | | |
+--------+ \----> +--------+ \----> +--------+ \----> +--------+ |
^ |
| |
| |
+--------+ |
| PTL0 | |
+--------+ |
PTL0 Page Table Level 0 (Page Directory) |
PTL1 Page Table Level 1 |
PTL2 Page Table Level 2 |
PTL3 Page Table Level 3 |
PTL0_INDEX Index into PTL0 |
PTL1_INDEX Index into PTL1 |
PTL2_INDEX Index into PTL2 |
PTL3_INDEX Index into PTL3 |
VADDR Virtual address for which mapping is looked up |
FRAME Physical address of memory frame to which VADDR is mapped |
On architectures whose hardware has fewer levels, PTL2 and, if need be, PTL1 are |
left out. TLB-only architectures are to define custom format for software page |
tables. |
/SPARTAN/trunk/src/Makefile.config |
---|
17,10 → 17,10 |
DEBUG_SPINLOCK=DEBUG_SPINLOCK |
# Uncomment if you want to compile in userspace support |
USERSPACE=__USERSPACE__ |
#USERSPACE=__USERSPACE__ |
# Uncomment if you want to run in the test mode |
TEST=__TEST__ |
#TEST=__TEST__ |
TEST_FILE=test.c |
/SPARTAN/trunk/arch/ia32/include/mm/page.h |
---|
37,6 → 37,21 |
#define KA2PA(x) ((x) - 0x80000000) |
#define PA2KA(x) ((x) + 0x80000000) |
/* |
* Implementation of generic 4-level page table interface. |
* IA-32 has 2-level page tables, so PTL1 and PTL2 are left out. |
*/ |
#define PTL0_INDEX_ARCH(vaddr) (((vaddr)>>22)&0x3ff) |
#define PTL1_INDEX_ARCH(vaddr) 0 |
#define PTL2_INDEX_ARCH(vaddr) 0 |
#define PTL3_INDEX_ARCH(vaddr) (((vaddr)>>12)&0x3ff) |
#define GET_PTL1_ADDRESS_ARCH(ptl0, i) ((pte_t *)((((pte_t *)(ptl0))[(i)].frame_address)<<12)) |
#define GET_PTL2_ADDRESS_ARCH(ptl1, i) (ptl1) |
#define GET_PTL3_ADDRESS_ARCH(ptl2, i) (ptl2) |
#define GET_FRAME_ADDRESS_ARCH(ptl3, i) ((__address)((((pte_t *)(ptl3))[(i)].frame_address)<<12)) |
struct page_specifier { |
unsigned present : 1; |
unsigned writeable : 1; |
50,6 → 65,8 |
unsigned frame_address : 20; |
} __attribute__ ((packed)); |
typedef struct page_specifier pte_t; |
extern void page_arch_init(void); |
#endif |