/SPARTAN/trunk/arch/ia64/src/fake.s |
---|
47,7 → 47,7 |
.global frame_arch_init |
.global map_page_to_frame |
.global memsetb |
.global panic |
.global panic_printf |
before_thread_runs_arch: |
userspace: |
68,6 → 68,6 |
frame_arch_init: |
map_page_to_frame: |
memsetb: |
panic: |
panic_printf: |
br.ret.sptk.many b0 |
/SPARTAN/trunk/arch/mips/src/exception.c |
---|
51,7 → 51,7 |
case EXC_Int: interrupt(); break; |
case EXC_TLBL: |
case EXC_TLBS: tlb_invalid(); break; |
default: panic(PANIC "unhandled exception %d\n", excno); break; |
default: panic("unhandled exception %d\n", excno); break; |
} |
if (THREAD) { |
/SPARTAN/trunk/arch/mips/src/cache.c |
---|
31,5 → 31,5 |
void cache_error(void) |
{ |
panic(PANIC "cache_error exception\n"); |
panic("cache_error exception\n"); |
} |
/SPARTAN/trunk/arch/mips/src/mm/tlb.c |
---|
41,12 → 41,12 |
main_bsp(); |
} |
panic(PANIC "tlb_refill exception\n"); |
panic("tlb_refill exception\n"); |
} |
void tlb_invalid(void) |
{ |
panic(PANIC "%X: TLB exception at %X", cp0_badvaddr_read(), THREAD ? THREAD->saved_epc : 0); |
panic("%X: TLB exception at %X", cp0_badvaddr_read(), THREAD ? THREAD->saved_epc : 0); |
} |
void tlb_invalidate(int asid) |
/SPARTAN/trunk/arch/mips/src/panic.s |
---|
32,9 → 32,9 |
.set noreorder |
.set nomacro |
.global panic |
.global panic_printf |
panic: |
panic_printf: |
jal printf |
nop |
j cpu_halt |
/SPARTAN/trunk/arch/mips/src/interrupt.c |
---|
75,7 → 75,7 |
case 0x3: |
case 0x4: |
case 0x5: |
case 0x6: panic(PANIC "unhandled interrupt %d\n", i); break; |
case 0x6: panic("unhandled interrupt %d\n", i); break; |
case 0x7: |
/* clear timer interrupt */ |
cp0_compare_write(cp0_compare_value); |
/SPARTAN/trunk/arch/ia32/src/debug/panic.s |
---|
27,8 → 27,8 |
# |
.text |
.global panic |
.global panic_printf |
panic: |
panic_printf: |
movl $halt,(%esp) # fake stack to make printf return to halt |
jmp printf |
/SPARTAN/trunk/arch/ia32/src/pm.c |
---|
143,7 → 143,7 |
else { |
tss_p = (struct tss *) malloc(sizeof(struct tss)); |
if (!tss_p) |
panic(PANIC "could not allocate TSS\n"); |
panic("could not allocate TSS\n"); |
} |
tss_initialize(tss_p); |
/SPARTAN/trunk/arch/ia32/src/smp/mps.c |
---|
469,7 → 469,7 |
* Prepare new GDT for CPU in question. |
*/ |
if (!(gdt_new = (struct descriptor *) malloc(GDT_ITEMS*sizeof(struct descriptor)))) |
panic(PANIC "couldn't allocate memory for GDT\n"); |
panic("couldn't allocate memory for GDT\n"); |
memcopy(gdt, gdt_new, GDT_ITEMS*sizeof(struct descriptor)); |
gdtr.base = (__address) gdt_new; |
/SPARTAN/trunk/arch/ia32/src/interrupt.c |
---|
28,6 → 28,7 |
#include <arch/interrupt.h> |
#include <print.h> |
#include <debug.h> |
#include <panic.h> |
#include <arch/i8259.h> |
#include <func.h> |
48,12 → 49,14 |
iroutine trap_register(__u8 n, iroutine f) |
{ |
ASSERT(n < IVT_ITEMS); |
iroutine old; |
old = ivt[n]; |
ivt[n] = f; |
return old; |
return old; |
} |
/* |
62,7 → 65,9 |
*/ |
void trap_dispatcher(__u8 n, __u32 stack[]) |
{ |
ivt[n](n,stack); |
ASSERT(n < IVT_ITEMS); |
ivt[n](n, stack); |
} |
void null_interrupt(__u8 n, __u32 stack[]) |
112,7 → 117,7 |
if (enable_irqs_function) |
enable_irqs_function(irqmask); |
else |
panic(PANIC "no enable_irqs_function\n"); |
panic("no enable_irqs_function\n"); |
} |
void trap_virtual_disable_irqs(__u16 irqmask) |
120,7 → 125,7 |
if (disable_irqs_function) |
disable_irqs_function(irqmask); |
else |
panic(PANIC "no disable_irqs_function\n"); |
panic("no disable_irqs_function\n"); |
} |
void trap_virtual_eoi(void) |
128,6 → 133,6 |
if (eoi_function) |
eoi_function(); |
else |
panic(PANIC "no eoi_function\n"); |
panic("no eoi_function\n"); |
} |