WebSVN – HelenOS-historic – Path Comparison – / – /SPARTAN/trunk/arch Rev 412 and /SPARTAN/trunk/arch Rev 413

Ignore whitespace Rev 412 → Rev 413

 /SPARTAN/trunk/arch/ia64/include/types.h
 ,7 → 40,7
 typedef __u64 __address;
-typedef __u64 pri_t;
+typedef __u64 ipl_t;
 typedef __u64 __native;

 /SPARTAN/trunk/arch/ia64/include/context.h
 ,7 → 95,7
      */
     __u64 pr;
-    pri_t pri;
+    ipl_t ipl;
 } __attribute__ ((packed));
 #endif

/SPARTAN/trunk/arch/ia64/src/context.S
134,6 → 134,7
* Restore application registers
*/

/* TODO: ensure RSE lazy mode */
mov ar.bspstore = loc4
mov ar.rnat = loc5
mov ar.pfs = loc0

 /SPARTAN/trunk/arch/ia64/src/dummy.s
 ,10 → 35,10
 .global arch_late_init
 .global cpu_identify
 .global cpu_print_report
-.global cpu_priority_high
-.global cpu_priority_low
-.global cpu_priority_read
-.global cpu_priority_restore
+.global interrupts_disable
+.global interrupts_enable
+.global interrupts_read
+.global interrupts_restore
 .global cpu_sleep
 .global dummy
 .global fpu_enable
 ,10 → 52,10
 arch_late_init:
 cpu_identify:
 cpu_print_report:
-cpu_priority_high:
-cpu_priority_low:
-cpu_priority_read:
-cpu_priority_restore:
+interrupts_disable:
+interrupts_enable:
+interrupts_read:
+interrupts_restore:
 cpu_sleep:
 fpu_init:
 fpu_enable:

 /SPARTAN/trunk/arch/ppc32/include/types.h
 ,7 → 40,7
 typedef __u32 __address;
-typedef __u32 pri_t;
+typedef __u32 ipl_t;
 typedef __u32 __native;

 /SPARTAN/trunk/arch/ppc32/include/asm.h
 ,14 → 32,16
 #include <arch/types.h>
 #include <config.h>
-/** Set priority level low
+/** Enable interrupts.
  *
  * Enable interrupts and return previous
  * value of EE.
+ *
+ * @return Old interrupt priority level.
  */
-static inline pri_t cpu_priority_low(void) {
-    pri_t v;
-    pri_t tmp;
+static inline ipl_t interrupts_enable(void) {
+    ipl_t v;
+    ipl_t tmp;
     __asm__ volatile (
         "mfmsr %0\n"
 ,14 → 53,16
     return v;
 }
-/** Set priority level high
+/** Disable interrupts.
  *
  * Disable interrupts and return previous
  * value of EE.
+ *
+ * @return Old interrupt priority level.
  */
-static inline pri_t cpu_priority_high(void) {
-    pri_t v;
-    pri_t tmp;
+static inline ipl_t interrupts_disable(void) {
+    ipl_t v;
+    ipl_t tmp;
     __asm__ volatile (
         "mfmsr %0\n"
 ,12 → 74,14
     return v;
 }
-/** Restore priority level
+/** Restore interrupt priority level.
  *
  * Restore EE.
+ *
+ * @param ipl Saved interrupt priority level.
  */
-static inline void cpu_priority_restore(pri_t pri) {
-    pri_t tmp;
+static inline void interrupts_restore(ipl_t ipl) {
+    ipl_t tmp;
     __asm__ volatile (
         "mfmsr %1\n"
 ,17 → 90,19
         "beq 0f\n"
         "mtmsr %0\n"
         "0:\n"
-        : "=r" (pri), "=r" (tmp)
-        : "0" (pri)
+        : "=r" (ipl), "=r" (tmp)
+        : "0" (ipl)
     );
 }
-/** Return raw priority level
+/** Return interrupt priority level.
  *
  * Return EE.
+ *
+ * @return Current interrupt priority level.
  */
-static inline pri_t cpu_priority_read(void) {
-    pri_t v;
+static inline ipl_t interrupts_read(void) {
+    ipl_t v;
     __asm__ volatile (
         "mfmsr %0\n"
         : "=r" (v)

 /SPARTAN/trunk/arch/ppc32/include/context.h
 ,7 → 67,7
     __u32 r30;
     __u32 r31;
     __u32 pc;
-    pri_t pri;
+    ipl_t ipl;
 } __attribute__ ((packed));
 #endif

 /SPARTAN/trunk/arch/amd64/include/asm.h
 ,13 → 82,15
         );
 }
-/** Set priority level low
+/** Enable interrupts.
  *
  * Enable interrupts and return previous
  * value of EFLAGS.
+ *
+ * @return Old interrupt priority level.
  */
-static inline pri_t cpu_priority_low(void) {
-    pri_t v;
+static inline ipl_t interrupts_enable(void) {
+    ipl_t v;
     __asm__ volatile (
         "pushfq\n"
         "popq %0\n"
 ,13 → 100,15
     return v;
 }
-/** Set priority level high
+/** Disable interrupts.
  *
  * Disable interrupts and return previous
  * value of EFLAGS.
+ *
+ * @return Old interrupt priority level.
  */
-static inline pri_t cpu_priority_high(void) {
-    pri_t v;
+static inline ipl_t interrupts_disable(void) {
+    ipl_t v;
     __asm__ volatile (
         "pushfq\n"
         "popq %0\n"
 ,24 → 118,28
     return v;
 }
-/** Restore priority level
+/** Restore interrupt priority level.
  *
  * Restore EFLAGS.
+ *
+ * @param ipl Saved interrupt priority level.
  */
-static inline void cpu_priority_restore(pri_t pri) {
+static inline void interrupts_restore(ipl_t ipl) {
     __asm__ volatile (
         "pushq %0\n"
         "popfq\n"
-        : : "r" (pri)
+        : : "r" (ipl)
         );
 }
-/** Return raw priority level
+/** Return interrupt priority level.
  *
  * Return EFLAFS.
+ *
+ * @return Current interrupt priority level.
  */
-static inline pri_t cpu_priority_read(void) {
-    pri_t v;
+static inline ipl_t interrupts_read(void) {
+    ipl_t v;
     __asm__ volatile (
         "pushfq\n"
         "popq %0\n"

 /SPARTAN/trunk/arch/amd64/include/context.h
 ,7 → 55,7
     __u64 r14;
     __u64 r15;
-    pri_t pri;
+    ipl_t ipl;
 } __attribute__ ((packed));
 #endif

 /SPARTAN/trunk/arch/amd64/include/types.h
 ,8 → 40,8
 typedef __u64 __address;
-/* Flags of processor (return value of cpu_priority_high()) */
-typedef __u64 pri_t;
+/* Flags of processor (return value of interrupts_disable()) */
+typedef __u64 ipl_t;
 typedef __u64 __native;

 /SPARTAN/trunk/arch/amd64/src/userspace.c
 ,9 → 41,9
  */
 void userspace(void)
 {
-    pri_t pri;
+    ipl_t ipl;
-    pri = cpu_priority_high();
+    ipl = interrupts_disable();
     __asm__ volatile (""
               "movq %0, %%rax;"
 ,7 → 57,7
               "pushq %%rdx;"
               "pushq %%rsi;"
               "iretq;"
-              : : "i" (gdtselector(UDATA_DES) | PL_USER), "i" (USTACK_ADDRESS+THREAD_STACK_SIZE), "r" (pri), "i" (gdtselector(UTEXT_DES) | PL_USER), "i" (UTEXT_ADDRESS));
+              : : "i" (gdtselector(UDATA_DES) | PL_USER), "i" (USTACK_ADDRESS+THREAD_STACK_SIZE), "r" (ipl), "i" (gdtselector(UTEXT_DES) | PL_USER), "i" (UTEXT_ADDRESS));
     /* Unreachable */
     for(;;);

 /SPARTAN/trunk/arch/amd64/src/interrupt.c
 ,7 → 108,7
 /*
  * Called directly from the assembler code.
- * CPU is cpu_priority_high().
+ * CPU is interrupts_disable()'d.
  */
 void trap_dispatcher(__u8 n, __native stack[])
 {

 /SPARTAN/trunk/arch/mips32/include/types.h
 ,7 → 45,7
 typedef __u32 __address;
-typedef __u32 pri_t;
+typedef __u32 ipl_t;
 typedef __u32 __native;

 /SPARTAN/trunk/arch/mips32/include/context.h
 ,7 → 62,7
     __u32 s8;
     __u32 gp;
-    __u32 pri;
+    ipl_t ipl;
 };
 #endif /* __ASM__ */

 /SPARTAN/trunk/arch/mips32/src/exception.c
 ,11 → 46,11
     /*
      * NOTE ON OPERATION ORDERING
      *
-     * On entry, cpu_priority_high() must be called before
+     * On entry, interrupts_disable() must be called before
      * exception bit is cleared.
      */
-    cpu_priority_high();
+    interrupts_disable();
     cp0_status_write(cp0_status_read() & ~ (cp0_status_exl_exception_bit |
                         cp0_status_um_bit));

 /SPARTAN/trunk/arch/mips32/src/mm/asid.c
 ,13 → 44,13
  */
 asid_t asid_get(void)
 {
-    pri_t pri;
+    ipl_t ipl;
     int i, j;
     count_t min;
     min = (unsigned) -1;
-    pri = cpu_priority_high();
+    ipl = interrupts_disable();
     spinlock_lock(&asid_usage_lock);
     for (i = ASID_START, j = ASID_START; i < ASIDS; i++) {
 ,7 → 65,7
     asid_usage[j]++;
     spinlock_unlock(&asid_usage_lock);
-    cpu_priority_restore(pri);
+    interrupts_restore(ipl);
     return i;
 }
 ,9 → 78,9
  */
 void asid_put(asid_t asid)
 {
-    pri_t pri;
+    ipl_t ipl;
-    pri = cpu_priority_high();
+    ipl = interrupts_disable();
     spinlock_lock(&asid_usage_lock);
     ASSERT(asid != ASID_INVALID);
 ,7 → 89,7
     asid_usage[asid]--;
     spinlock_unlock(&asid_usage_lock);
-    cpu_priority_restore(pri);
+    interrupts_restore(ipl);
 }
 /** Find out whether ASID is used by more address spaces
 ,11 → 103,11
 bool asid_has_conflicts(asid_t asid)
 {
     bool has_conflicts = false;
-    pri_t pri;
+    ipl_t ipl;
     ASSERT(asid != ASID_INVALID);
-    pri = cpu_priority_high();
+    ipl = interrupts_disable();
     spinlock_lock(&asid_usage_lock);
     if (asid_usage[asid] > 1)
 ,7 → 114,7
         has_conflicts = true;
     spinlock_unlock(&asid_usage_lock);
-    cpu_priority_restore(pri);
+    interrupts_restore(ipl);
     return has_conflicts;
 }

 /SPARTAN/trunk/arch/mips32/src/mm/tlb.c
 ,12 → 315,12
 void tlb_invalidate(asid_t asid)
 {
     entry_hi_t hi;
-    pri_t pri;
+    ipl_t ipl;
     int i;
     ASSERT(asid != ASID_INVALID);
-    pri = cpu_priority_high();
+    ipl = interrupts_disable();
     for (i = 0; i < TLB_SIZE; i++) {
         cp0_index_write(i);
 ,7 → 336,7
         }
     }
-    cpu_priority_restore(pri);
+    interrupts_restore(ipl);
 }
 /** Try to find PTE for faulting address

 /SPARTAN/trunk/arch/mips32/src/mm/vm.c
 ,14 → 41,14
 void vm_install_arch(vm_t *vm)
 {
     entry_hi_t hi;
-    pri_t pri;
+    ipl_t ipl;
     hi.value = cp0_entry_hi_read();
-    pri = cpu_priority_high();
+    ipl = interrupts_disable();
     spinlock_lock(&vm->lock);
     hi.asid = vm->asid;
     cp0_entry_hi_write(hi.value);
     spinlock_lock(&vm->unlock);
-    cpu_priority_restore(pri);
+    interrupts_restore(ipl);
 }

 /SPARTAN/trunk/arch/mips32/src/interrupt.c
 ,26 → 52,42
            pstate->ra,rasymbol);
 }
-pri_t cpu_priority_high(void)
+/** Disable interrupts.
+ *
+ * @return Old interrupt priority level.
+ */
+ipl_t interrupts_disable(void)
 {
-    pri_t pri = (pri_t) cp0_status_read();
-    cp0_status_write(pri & ~cp0_status_ie_enabled_bit);
-    return pri;
+    ipl_t ipl = (ipl_t) cp0_status_read();
+    cp0_status_write(ipl & ~cp0_status_ie_enabled_bit);
+    return ipl;
 }
-pri_t cpu_priority_low(void)
+/** Enable interrupts.
+ *
+ * @return Old interrupt priority level.
+ */
+ipl_t interrupts_enable(void)
 {
-    pri_t pri = (pri_t) cp0_status_read();
-    cp0_status_write(pri | cp0_status_ie_enabled_bit);
-    return pri;
+    ipl_t ipl = (ipl_t) cp0_status_read();
+    cp0_status_write(ipl | cp0_status_ie_enabled_bit);
+    return ipl;
 }
-void cpu_priority_restore(pri_t pri)
+/** Restore interrupt priority level.
+ *
+ * @param ipl Saved interrupt priority level.
+ */
+void interrupts_restore(ipl_t ipl)
 {
-    cp0_status_write(cp0_status_read() | (pri & cp0_status_ie_enabled_bit));
+    cp0_status_write(cp0_status_read() | (ipl & cp0_status_ie_enabled_bit));
 }
-pri_t cpu_priority_read(void)
+/** Read interrupt priority level.
+ *
+ * @return Current interrupt priority level.
+ */
+ipl_t interrupts_read(void)
 {
     return cp0_status_read();
 }

 /SPARTAN/trunk/arch/mips32/src/drivers/arc.c
 ,11 → 175,11
 void arc_putchar(char ch)
 {
     __u32 cnt;
-    pri_t pri;
+    ipl_t ipl;
     /* TODO: Should be spinlock? */
-    pri = cpu_priority_high();
+    ipl = interrupts_disable();
     arc_entry->write(1, &ch, 1, &cnt);
-    cpu_priority_restore(pri);
+    interrupts_restore(ipl);
 }

 /SPARTAN/trunk/arch/mips32/src/mips32.c
 ,7 → 52,7
 void arch_pre_mm_init(void)
 {
     /* It is not assumed by default */
-    cpu_priority_high();
+    interrupts_disable();
     init_arc();

 /SPARTAN/trunk/arch/ia32/include/types.h
 ,7 → 40,7
 typedef __u32 __address;
-typedef __u32 pri_t;
+typedef __u32 ipl_t;
 typedef __u32 __native;

 /SPARTAN/trunk/arch/ia32/include/asm.h
 ,13 → 131,15
  */
 static inline __u32 inl(__u16 port) { __u32 val; __asm__ volatile ("inl %w1, %l0 \n" : "=a" (val) : "d" (port) ); return val; }
-/** Set priority level low
+/** Enable interrupts.
  *
  * Enable interrupts and return previous
  * value of EFLAGS.
+ *
+ * @return Old interrupt priority level.
  */
-static inline pri_t cpu_priority_low(void) {
-    pri_t v;
+static inline ipl_t interrupts_enable(void) {
+    ipl_t v;
     __asm__ volatile (
         "pushf\n\t"
         "popl %0\n\t"
 ,13 → 149,15
     return v;
 }
-/** Set priority level high
+/** Disable interrupts.
  *
  * Disable interrupts and return previous
  * value of EFLAGS.
+ *
+ * @return Old interrupt priority level.
  */
-static inline pri_t cpu_priority_high(void) {
-    pri_t v;
+static inline ipl_t interrupts_disable(void) {
+    ipl_t v;
     __asm__ volatile (
         "pushf\n\t"
         "popl %0\n\t"
 ,24 → 167,26
     return v;
 }
-/** Restore priority level
+/** Restore interrupt priority level.
  *
  * Restore EFLAGS.
+ *
+ * @param ipl Saved interrupt priority level.
  */
-static inline void cpu_priority_restore(pri_t pri) {
+static inline void interrupts_restore(ipl_t ipl) {
     __asm__ volatile (
         "pushl %0\n\t"
         "popf\n"
-        : : "r" (pri)
+        : : "r" (ipl)
     );
 }
-/** Return raw priority level
+/** Return interrupt priority level.
  *
- * Return EFLAFS.
+ * @return EFLAFS.
  */
-static inline pri_t cpu_priority_read(void) {
-    pri_t v;
+static inline ipl_t interrupts_read(void) {
+    ipl_t v;
     __asm__ volatile (
         "pushf\n\t"
         "popl %0\n"

 /SPARTAN/trunk/arch/ia32/include/context.h
 ,7 → 52,7
     __u32 esi;
     __u32 edi;
     __u32 ebp;
-    __u32 pri;
+    ipl_t ipl;
 } __attribute__ ((packed));
 #endif

 /SPARTAN/trunk/arch/ia32/src/userspace.c
 ,9 → 41,9
  */
 void userspace(void)
 {
-    pri_t pri;
+    ipl_t ipl;
-    pri = cpu_priority_high();
+    ipl = interrupts_disable();
     __asm__ volatile (
         /* CLNT */
 ,7 → 60,7
         "pushl %4\n"
         "iret"
         :
-        : "i" (selector(UDATA_DES) | PL_USER), "r" (USTACK_ADDRESS+(THREAD_STACK_SIZE)), "r" (pri), "i" (selector(UTEXT_DES) | PL_USER), "i" (UTEXT_ADDRESS)
+        : "i" (selector(UDATA_DES) | PL_USER), "r" (USTACK_ADDRESS+(THREAD_STACK_SIZE)), "r" (ipl), "i" (selector(UTEXT_DES) | PL_USER), "i" (UTEXT_ADDRESS)
         : "eax");
     /* Unreachable */

 /SPARTAN/trunk/arch/ia32/src/interrupt.c
 ,7 → 79,7
 /*
  * Called directly from the assembler code.
- * CPU is cpu_priority_high().
+ * CPU is interrupts_disable()'d.
  */
 void trap_dispatcher(__u8 n, __native stack[])
 {

 /SPARTAN/trunk/arch/ia32/src/drivers/ega.c
 ,9 → 80,9
 void ega_putchar(const char ch)
 {
-    pri_t pri;
+    ipl_t ipl;
-    pri = cpu_priority_high();
+    ipl = interrupts_disable();
     spinlock_lock(&egalock);
     switch (ch) {
 ,7 → 101,7
     ega_move_cursor();
     spinlock_unlock(&egalock);
-    cpu_priority_restore(pri);
+    interrupts_restore(ipl);
 }
 void ega_move_cursor(void)

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Ignore whitespace Rev 412 → Rev 413