/SPARTAN/trunk/arch/amd64/include/pm.h |
---|
86,16 → 86,16 |
unsigned base_0_15: 16; |
unsigned base_16_23: 8; |
unsigned type: 4; |
unsigned reserve1 : 1; |
unsigned : 1; |
unsigned dpl : 2; |
unsigned present : 1; |
unsigned limit_16_19: 4; |
unsigned available: 1; |
unsigned reserve2: 2; |
unsigned : 2; |
unsigned granularity : 1; |
unsigned base_24_31: 8; |
unsigned base_32_63 : 32; |
unsigned reserve3 : 32; |
unsigned : 32; |
} __attribute__ ((packed)); |
struct idescriptor { |
107,8 → 107,8 |
unsigned dpl: 2; |
unsigned present : 1; |
unsigned offset_16_31: 16; |
unsigned offset_32_63: 16; |
unsigned reserved : 32; |
unsigned offset_32_63: 32; |
unsigned : 32; |
} __attribute__ ((packed)); |
struct ptr_16_64 { |
/SPARTAN/trunk/arch/amd64/include/asm.h |
---|
36,7 → 36,6 |
void asm_delay_loop(__u32 t); |
void asm_fake_loop(__u32 t); |
/* TODO: implement the real stuff */ |
static inline __address get_stack_base(void) |
{ |
44,6 → 43,7 |
} |
static inline void cpu_sleep(void) { __asm__("hlt"); }; |
static inline void cpu_halt(void) { __asm__("hlt"); }; |
static inline __u8 inb(__u16 port) |
137,7 → 137,7 |
* |
* @return Value read. |
*/ |
static inline __u32 read_cr2(void) { __u64 v; __asm__ volatile ("movq %%cr2,%0" : "=r" (v)); return v; } |
static inline __u64 read_cr2(void) { __u64 v; __asm__ volatile ("movq %%cr2,%0" : "=r" (v)); return v; } |
/** Write CR3 |
* |
153,16 → 153,9 |
* |
* @return Value read. |
*/ |
static inline __u32 read_cr3(void) { __u64 v; __asm__ volatile ("movq %%cr3,%0" : "=r" (v)); return v; } |
static inline __u64 read_cr3(void) { __u64 v; __asm__ volatile ("movq %%cr3,%0" : "=r" (v)); return v; } |
/** Set priority level low |
* |
* Enable interrupts and return previous |
* value of EFLAGS. |
*/ |
extern size_t interrupt_handler_size; |
extern void interrupt_handlers(void); |
/SPARTAN/trunk/arch/amd64/Makefile.inc |
---|
30,4 → 30,5 |
arch/interrupt.c \ |
arch/mm/frame.c \ |
arch/mm/page.c \ |
arch/mm/tlb.c |
arch/mm/tlb.c \ |
arch/asm_utils.S |
/SPARTAN/trunk/arch/amd64/src/asm_utils.S |
---|
0,0 → 1,144 |
# |
# Copyright (C) 2005 Ondrej Palkovsky |
# All rights reserved. |
# |
# Redistribution and use in source and binary forms, with or without |
# modification, are permitted provided that the following conditions |
# are met: |
# |
# - Redistributions of source code must retain the above copyright |
# notice, this list of conditions and the following disclaimer. |
# - Redistributions in binary form must reproduce the above copyright |
# notice, this list of conditions and the following disclaimer in the |
# documentation and/or other materials provided with the distribution. |
# - The name of the author may not be used to endorse or promote products |
# derived from this software without specific prior written permission. |
# |
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
# |
# Mask for interrupts 0 - 31 (bits 0 - 31) where 0 means that int has no error word |
# and 1 means interrupt with error word |
#define ERROR_WORD_INTERRUPT_LIST 0x00027D00 |
#define __ASM__ |
#include <arch/pm.h> |
.text |
.global interrupt_handlers |
.global panic_printf |
panic_printf: |
movq $halt, (%rsp) |
jmp printf |
# Push all general purpose registers on stack except %rbp, %rsp |
.macro push_all_gpr |
pushq %rax |
pushq %rbx |
pushq %rcx |
pushq %rdx |
pushq %rsi |
pushq %rdi |
pushq %r8 |
pushq %r9 |
pushq %r10 |
pushq %r11 |
pushq %r12 |
pushq %r13 |
pushq %r14 |
pushq %r15 |
.endm |
.macro pop_all_gpr |
popq %r15 |
popq %r14 |
popq %r13 |
popq %r12 |
popq %r11 |
popq %r10 |
popq %r9 |
popq %r8 |
popq %rdi |
popq %rsi |
popq %rdx |
popq %rcx |
popq %rbx |
popq %rax |
.endm |
## Declare interrupt handlers |
# |
# Declare interrupt handlers for n interrupt |
# vectors starting at vector i. |
# |
# The handlers setup data segment registers |
# and call trap_dispatcher(). |
# |
.macro handler i n |
pushq %rbp |
movq %rsp,%rbp |
push_all_gpr |
# trap_dispatcher(i, stack) |
movq $(\i),%rdi # %rdi - first parameter |
movq %rbp, %rsi |
addq $8, %rsi # %rsi - second parameter - original stack |
call trap_dispatcher |
# Test if this is interrupt with error word or not |
mov $\i,%cl; |
movl $1,%eax; |
test $0xe0,%cl; |
jnz 0f; |
and $0x1f,%cl; |
shl %cl,%eax; |
and $ERROR_WORD_INTERRUPT_LIST,%eax; |
jz 0f; |
# Return with error word |
pop_all_gpr |
popq %rbp; |
add $8,%esp; # Skip error word |
iretq |
0: |
# Return with no error word |
pop_all_gpr |
popq %rbp |
iretq |
.if (\n-\i)-1 |
handler "(\i+1)",\n |
.endif |
.endm |
interrupt_handlers: |
h_start: |
handler 0 IDT_ITEMS |
# handler 64 128 |
# handler 128 192 |
# handler 192 256 |
h_end: |
.data |
.global interrupt_handler_size |
interrupt_handler_size: .long (h_end-h_start)/IDT_ITEMS |
/SPARTAN/trunk/arch/amd64/src/boot/memmap.S |
---|
116,7 → 116,7 |
#memory size in 1 kb chunks |
e801memorysize: |
.long 0 |
.long 0x0 |
e820counter: |
.byte 0x0 |
/SPARTAN/trunk/arch/amd64/src/dummy.s |
---|
30,7 → 30,6 |
.global userspace |
.global before_thread_runs_arch |
.global panic_printf |
.global cpu_identify |
.global cpu_arch_init |
.global cpu_sleep |
37,14 → 36,11 |
.global cpu_print_report |
.global arch_late_init |
.global calibrate_delay_loop |
.global cpu_halt |
.global dummy |
.global rdtsc |
.global reset_TS_flag |
.global fpu_init |
.global interrupt_handler_size |
.global interrupt_handlers |
.global memory_print_map |
.global get_memory_size |
52,13 → 48,10 |
movq $4*1024*1024, %rax |
ret |
interrupt_handler_size: |
interrupt_handlers: |
rdtsc: |
before_thread_runs_arch: |
userspace: |
calibrate_delay_loop: |
panic_printf: |
cpu_identify: |
cpu_arch_init: |
cpu_sleep: |
65,7 → 58,6 |
cpu_print_report: |
arch_late_init: |
calibrate_delay_loop: |
cpu_halt: |
reset_TS_flag: |
fpu_init: |
memory_print_map: |
/SPARTAN/trunk/arch/amd64/src/pm.c |
---|
180,7 → 180,7 |
} |
trap_register(13, gp_fault); |
trap_register( 7, nm_fault); |
trap_register(12, ss_fault); |
trap_register(12, ss_fault); |
} |
/SPARTAN/trunk/arch/ia32/src/interrupt.c |
---|
83,7 → 83,6 |
printf("%%eax=%L, %%ebx=%L, %%ecx=%L, %%edx=%L,\n%%edi=%L, %%esi=%L, %%ebp=%L, %%esp=%L\n", stack[-2], stack[-5], stack[-3], stack[-4], stack[-9], stack[-8], stack[-1], stack); |
printf("stack: %X, %X, %X, %X\n", stack[4], stack[5], stack[6], stack[7]); |
panic("general protection fault\n"); |
stack[1]++; |
} |
void ss_fault(__u8 n, __native stack[]) |