/SPARTAN/trunk/arch/mips32/src/exception.c |
---|
46,11 → 46,11 |
/* |
* NOTE ON OPERATION ORDERING |
* |
* On entry, cpu_priority_high() must be called before |
* On entry, interrupts_disable() must be called before |
* exception bit is cleared. |
*/ |
cpu_priority_high(); |
interrupts_disable(); |
cp0_status_write(cp0_status_read() & ~ (cp0_status_exl_exception_bit | |
cp0_status_um_bit)); |
/SPARTAN/trunk/arch/mips32/src/mm/asid.c |
---|
44,13 → 44,13 |
*/ |
asid_t asid_get(void) |
{ |
pri_t pri; |
ipl_t ipl; |
int i, j; |
count_t min; |
min = (unsigned) -1; |
pri = cpu_priority_high(); |
ipl = interrupts_disable(); |
spinlock_lock(&asid_usage_lock); |
for (i = ASID_START, j = ASID_START; i < ASIDS; i++) { |
65,7 → 65,7 |
asid_usage[j]++; |
spinlock_unlock(&asid_usage_lock); |
cpu_priority_restore(pri); |
interrupts_restore(ipl); |
return i; |
} |
78,9 → 78,9 |
*/ |
void asid_put(asid_t asid) |
{ |
pri_t pri; |
ipl_t ipl; |
pri = cpu_priority_high(); |
ipl = interrupts_disable(); |
spinlock_lock(&asid_usage_lock); |
ASSERT(asid != ASID_INVALID); |
89,7 → 89,7 |
asid_usage[asid]--; |
spinlock_unlock(&asid_usage_lock); |
cpu_priority_restore(pri); |
interrupts_restore(ipl); |
} |
/** Find out whether ASID is used by more address spaces |
103,11 → 103,11 |
bool asid_has_conflicts(asid_t asid) |
{ |
bool has_conflicts = false; |
pri_t pri; |
ipl_t ipl; |
ASSERT(asid != ASID_INVALID); |
pri = cpu_priority_high(); |
ipl = interrupts_disable(); |
spinlock_lock(&asid_usage_lock); |
if (asid_usage[asid] > 1) |
114,7 → 114,7 |
has_conflicts = true; |
spinlock_unlock(&asid_usage_lock); |
cpu_priority_restore(pri); |
interrupts_restore(ipl); |
return has_conflicts; |
} |
/SPARTAN/trunk/arch/mips32/src/mm/tlb.c |
---|
315,12 → 315,12 |
void tlb_invalidate(asid_t asid) |
{ |
entry_hi_t hi; |
pri_t pri; |
ipl_t ipl; |
int i; |
ASSERT(asid != ASID_INVALID); |
pri = cpu_priority_high(); |
ipl = interrupts_disable(); |
for (i = 0; i < TLB_SIZE; i++) { |
cp0_index_write(i); |
336,7 → 336,7 |
} |
} |
cpu_priority_restore(pri); |
interrupts_restore(ipl); |
} |
/** Try to find PTE for faulting address |
/SPARTAN/trunk/arch/mips32/src/mm/vm.c |
---|
41,14 → 41,14 |
void vm_install_arch(vm_t *vm) |
{ |
entry_hi_t hi; |
pri_t pri; |
ipl_t ipl; |
hi.value = cp0_entry_hi_read(); |
pri = cpu_priority_high(); |
ipl = interrupts_disable(); |
spinlock_lock(&vm->lock); |
hi.asid = vm->asid; |
cp0_entry_hi_write(hi.value); |
spinlock_lock(&vm->unlock); |
cpu_priority_restore(pri); |
interrupts_restore(ipl); |
} |
/SPARTAN/trunk/arch/mips32/src/interrupt.c |
---|
52,26 → 52,42 |
pstate->ra,rasymbol); |
} |
pri_t cpu_priority_high(void) |
/** Disable interrupts. |
* |
* @return Old interrupt priority level. |
*/ |
ipl_t interrupts_disable(void) |
{ |
pri_t pri = (pri_t) cp0_status_read(); |
cp0_status_write(pri & ~cp0_status_ie_enabled_bit); |
return pri; |
ipl_t ipl = (ipl_t) cp0_status_read(); |
cp0_status_write(ipl & ~cp0_status_ie_enabled_bit); |
return ipl; |
} |
pri_t cpu_priority_low(void) |
/** Enable interrupts. |
* |
* @return Old interrupt priority level. |
*/ |
ipl_t interrupts_enable(void) |
{ |
pri_t pri = (pri_t) cp0_status_read(); |
cp0_status_write(pri | cp0_status_ie_enabled_bit); |
return pri; |
ipl_t ipl = (ipl_t) cp0_status_read(); |
cp0_status_write(ipl | cp0_status_ie_enabled_bit); |
return ipl; |
} |
void cpu_priority_restore(pri_t pri) |
/** Restore interrupt priority level. |
* |
* @param ipl Saved interrupt priority level. |
*/ |
void interrupts_restore(ipl_t ipl) |
{ |
cp0_status_write(cp0_status_read() | (pri & cp0_status_ie_enabled_bit)); |
cp0_status_write(cp0_status_read() | (ipl & cp0_status_ie_enabled_bit)); |
} |
pri_t cpu_priority_read(void) |
/** Read interrupt priority level. |
* |
* @return Current interrupt priority level. |
*/ |
ipl_t interrupts_read(void) |
{ |
return cp0_status_read(); |
} |
/SPARTAN/trunk/arch/mips32/src/drivers/arc.c |
---|
175,11 → 175,11 |
void arc_putchar(char ch) |
{ |
__u32 cnt; |
pri_t pri; |
ipl_t ipl; |
/* TODO: Should be spinlock? */ |
pri = cpu_priority_high(); |
ipl = interrupts_disable(); |
arc_entry->write(1, &ch, 1, &cnt); |
cpu_priority_restore(pri); |
interrupts_restore(ipl); |
} |
/SPARTAN/trunk/arch/mips32/src/mips32.c |
---|
52,7 → 52,7 |
void arch_pre_mm_init(void) |
{ |
/* It is not assumed by default */ |
cpu_priority_high(); |
interrupts_disable(); |
init_arc(); |