/SPARTAN/trunk/arch/mips32/include/cp0.h |
---|
52,32 → 52,13 |
*/ |
#define cp0_compare_value 10000 |
static inline void tlbp(void) |
{ |
__asm__ volatile ("tlbp"); |
} |
static inline void tlbr(void) |
{ |
__asm__ volatile ("tlbr"); |
} |
static inline void tlbwi(void) |
{ |
__asm__ volatile ("tlbwi"); |
} |
static inline void tlbwr(void) |
{ |
__asm__ volatile ("tlbwr"); |
} |
#define cp0_mask_all_int() cp0_status_write(cp0_status_read() & ~(cp0_status_im_mask)) |
#define cp0_unmask_all_int() cp0_status_write(cp0_status_read() | cp0_status_im_mask) |
#define cp0_mask_int(it) cp0_status_write(cp0_status_read() & ~(1<<(cp0_status_im_shift+(it)))) |
#define cp0_unmask_int(it) cp0_status_write(cp0_status_read() | (1<<(cp0_status_im_shift+(it)))) |
extern __u32 cp0_index_read(void); |
extern void cp0_idnex_write(__u32 val); |
extern void cp0_index_write(__u32 val); |
extern __u32 cp0_random_read(void); |
/SPARTAN/trunk/arch/mips32/include/mm/tlb.h |
---|
31,6 → 31,13 |
#include <arch/exception.h> |
#define TLB_SIZE 48 |
#define TLB_WIRED 1 |
#define TLB_KSTACK_WIRED_INDEX 0 |
#define TLB_PAGE_MASK_16K (0x3<<13) |
#define PAGE_UNCACHED 2 |
#define PAGE_CACHEABLE_EXC_WRITE 5 |
65,7 → 72,35 |
typedef struct entry_lo pte_t; |
/** Read Indexed TLB Entry |
* |
* Read Indexed TLB Entry. |
*/ |
static inline void tlbr(void) |
{ |
__asm__ volatile ("tlbr\n\t"); |
} |
/** Write Indexed TLB Entry |
* |
* Write Indexed TLB Entry. |
*/ |
static inline void tlbwi(void) |
{ |
__asm__ volatile ("tlbwi\n\t"); |
} |
/** Write Random TLB Entry |
* |
* Write Random TLB Entry. |
*/ |
static inline void tlbwr(void) |
{ |
__asm__ volatile ("tlbwr\n\t"); |
} |
extern void tlb_invalid(struct exception_regdump *pstate); |
extern void tlb_refill(struct exception_regdump *pstate); |
extern void tlb_modified(struct exception_regdump *pstate); |
#endif |