/SPARTAN/trunk/arch/mips/boot/boot.s |
---|
35,9 → 35,9 |
start: |
# move 0x80000000 to reg $8 |
lui $8, 0x8000 |
# prepare stack |
lui $29, 0x8100 |
j $8 |
nop |
/SPARTAN/trunk/arch/mips/include/mm/page.h |
---|
59,13 → 59,13 |
#define PTL2_INDEX_ARCH(vaddr) 0 |
#define PTL3_INDEX_ARCH(vaddr) (((vaddr)>>14)&0xfff) |
#define GET_PTL0_ADDRESS_ARCH() (PTL0) |
#define GET_PTL0_ADDRESS_ARCH() (PTL0) |
#define SET_PTL0_ADDRESS_ARCH(ptl0) (PTL0 = (pte_t *)(ptl0)) |
#define GET_PTL1_ADDRESS_ARCH(ptl0, i) (((pte_t *)(ptl0))[(i)].pfn<<14) |
#define GET_PTL2_ADDRESS_ARCH(ptl1, i) (ptl1) |
#define GET_PTL3_ADDRESS_ARCH(ptl2, i) (ptl2) |
#define GET_FRAME_ADDRESS_ARCH(ptl3, i) (((pte_t *)(ptl3))[(i)].pfn<<14) |
#define GET_PTL1_ADDRESS_ARCH(ptl0, i) (((pte_t *)(ptl0))[(i)].pfn<<14) |
#define GET_PTL2_ADDRESS_ARCH(ptl1, i) (ptl1) |
#define GET_PTL3_ADDRESS_ARCH(ptl2, i) (ptl2) |
#define GET_FRAME_ADDRESS_ARCH(ptl3, i) (((pte_t *)(ptl3))[(i)].pfn<<14) |
#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) (((pte_t *)(ptl0))[(i)].pfn = (a)>>14) |
#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a) |
72,10 → 72,10 |
#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a) |
#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) (((pte_t *)(ptl3))[(i)].pfn = (a)>>14) |
#define GET_PTL1_FLAGS_ARCH(ptl0, i) get_pt_flags((pte_t *)(ptl0), (index_t)(i)) |
#define GET_PTL2_FLAGS_ARCH(ptl1, i) PAGE_PRESENT |
#define GET_PTL3_FLAGS_ARCH(ptl2, i) PAGE_PRESENT |
#define GET_FRAME_FLAGS_ARCH(ptl3, i) get_pt_flags((pte_t *)(ptl3), (index_t)(i)) |
#define GET_PTL1_FLAGS_ARCH(ptl0, i) get_pt_flags((pte_t *)(ptl0), (index_t)(i)) |
#define GET_PTL2_FLAGS_ARCH(ptl1, i) PAGE_PRESENT |
#define GET_PTL3_FLAGS_ARCH(ptl2, i) PAGE_PRESENT |
#define GET_FRAME_FLAGS_ARCH(ptl3, i) get_pt_flags((pte_t *)(ptl3), (index_t)(i)) |
#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) set_pt_flags((pte_t *)(ptl0), (index_t)(i), (x)) |
#define SET_PTL2_FLAGS_ARCH(ptl1, i, x) |
/SPARTAN/trunk/arch/mips/include/context.h |
---|
35,39 → 35,39 |
struct context { |
__u32 r0; |
__u32 r1; |
__u32 r2; |
__u32 r3; |
__u32 r4; |
__u32 r5; |
__u32 r6; |
__u32 r7; |
__u32 r8; |
__u32 r9; |
__u32 r10; |
__u32 r11; |
__u32 r12; |
__u32 r13; |
__u32 r14; |
__u32 r15; |
__u32 r16; |
__u32 r17; |
__u32 r18; |
__u32 r19; |
__u32 r20; |
__u32 r21; |
__u32 r22; |
__u32 r23; |
__u32 r24; |
__u32 r25; |
__u32 r26; |
__u32 r27; |
__u32 r28; |
__u32 sp; |
__u32 r30; |
__u32 pc; |
__u32 pri; |
__u32 r0; |
__u32 r1; |
__u32 r2; |
__u32 r3; |
__u32 r4; |
__u32 r5; |
__u32 r6; |
__u32 r7; |
__u32 r8; |
__u32 r9; |
__u32 r10; |
__u32 r11; |
__u32 r12; |
__u32 r13; |
__u32 r14; |
__u32 r15; |
__u32 r16; |
__u32 r17; |
__u32 r18; |
__u32 r19; |
__u32 r20; |
__u32 r21; |
__u32 r22; |
__u32 r23; |
__u32 r24; |
__u32 r25; |
__u32 r26; |
__u32 r27; |
__u32 r28; |
__u32 sp; |
__u32 r30; |
__u32 pc; |
__u32 pri; |
}; |
#endif |
/SPARTAN/trunk/arch/mips/include/cpu.h |
---|
34,8 → 34,8 |
#define CPU_ID_ARCH 0 |
struct cpu_arch { |
int imp_num; |
int rev_num; |
int imp_num; |
int rev_num; |
}; |
#endif |
/SPARTAN/trunk/arch/mips/src/cpu/cpu.c |
---|
39,42 → 39,42 |
char *vendor; |
char *model; |
} imp_data[] = { |
{ "Invalid", "Invalid" }, /* 0x00 */ |
{ "MIPS", "R2000" }, /* 0x01 */ |
{ "MIPS", "R3000" }, /* 0x02 */ |
{ "MIPS", "R6000" }, /* 0x03 */ |
{ "MIPS", " R4000/R4400" }, /* 0x04 */ |
{ "LSI Logic", "R3000" }, /* 0x05 */ |
{ "MIPS", "R6000A" }, /* 0x06 */ |
{ "IDT", "3051/3052" }, /* 0x07 */ |
{ "Invalid", "Invalid" }, /* 0x08 */ |
{ "MIPS", "R10000/T5" }, /* 0x09 */ |
{ "MIPS", "R4200" }, /* 0x0a */ |
{ "Unknown", "Unknown" }, /* 0x0b */ |
{ "Unknown", "Unknown" }, /* 0x0c */ |
{ "Invalid", "Invalid" }, /* 0x0d */ |
{ "Invalid", "Invalid" }, /* 0x0e */ |
{ "Invalid", "Invalid" }, /* 0x0f */ |
{ "MIPS", "R8000" }, /* 0x10 */ |
{ "Invalid", "Invalid" }, /* 0x11 */ |
{ "Invalid", "Invalid" }, /* 0x12 */ |
{ "Invalid", "Invalid" }, /* 0x13 */ |
{ "Invalid", "Invalid" }, /* 0x14 */ |
{ "Invalid", "Invalid" }, /* 0x15 */ |
{ "Invalid", "Invalid" }, /* 0x16 */ |
{ "Invalid", "Invalid" }, /* 0x17 */ |
{ "Invalid", "Invalid" }, /* 0x18 */ |
{ "Invalid", "Invalid" }, /* 0x19 */ |
{ "Invalid", "Invalid" }, /* 0x1a */ |
{ "Invalid", "Invalid" }, /* 0x1b */ |
{ "Invalid", "Invalid" }, /* 0x1c */ |
{ "Invalid", "Invalid" }, /* 0x1d */ |
{ "Invalid", "Invalid" }, /* 0x1e */ |
{ "Invalid", "Invalid" }, /* 0x1f */ |
{ "QED", "R4600" }, /* 0x20 */ |
{ "Sony", "R3000" }, /* 0x21 */ |
{ "Toshiba", "R3000" }, /* 0x22 */ |
{ "NKK", "R3000" } /* 0x23 */ |
{ "Invalid", "Invalid" }, /* 0x00 */ |
{ "MIPS", "R2000" }, /* 0x01 */ |
{ "MIPS", "R3000" }, /* 0x02 */ |
{ "MIPS", "R6000" }, /* 0x03 */ |
{ "MIPS", " R4000/R4400" }, /* 0x04 */ |
{ "LSI Logic", "R3000" }, /* 0x05 */ |
{ "MIPS", "R6000A" }, /* 0x06 */ |
{ "IDT", "3051/3052" }, /* 0x07 */ |
{ "Invalid", "Invalid" }, /* 0x08 */ |
{ "MIPS", "R10000/T5" }, /* 0x09 */ |
{ "MIPS", "R4200" }, /* 0x0a */ |
{ "Unknown", "Unknown" }, /* 0x0b */ |
{ "Unknown", "Unknown" }, /* 0x0c */ |
{ "Invalid", "Invalid" }, /* 0x0d */ |
{ "Invalid", "Invalid" }, /* 0x0e */ |
{ "Invalid", "Invalid" }, /* 0x0f */ |
{ "MIPS", "R8000" }, /* 0x10 */ |
{ "Invalid", "Invalid" }, /* 0x11 */ |
{ "Invalid", "Invalid" }, /* 0x12 */ |
{ "Invalid", "Invalid" }, /* 0x13 */ |
{ "Invalid", "Invalid" }, /* 0x14 */ |
{ "Invalid", "Invalid" }, /* 0x15 */ |
{ "Invalid", "Invalid" }, /* 0x16 */ |
{ "Invalid", "Invalid" }, /* 0x17 */ |
{ "Invalid", "Invalid" }, /* 0x18 */ |
{ "Invalid", "Invalid" }, /* 0x19 */ |
{ "Invalid", "Invalid" }, /* 0x1a */ |
{ "Invalid", "Invalid" }, /* 0x1b */ |
{ "Invalid", "Invalid" }, /* 0x1c */ |
{ "Invalid", "Invalid" }, /* 0x1d */ |
{ "Invalid", "Invalid" }, /* 0x1e */ |
{ "Invalid", "Invalid" }, /* 0x1f */ |
{ "QED", "R4600" }, /* 0x20 */ |
{ "Sony", "R3000" }, /* 0x21 */ |
{ "Toshiba", "R3000" }, /* 0x22 */ |
{ "NKK", "R3000" } /* 0x23 */ |
}; |
void cpu_arch_init(void) |
/SPARTAN/trunk/arch/mips/src/mips.c |
---|
37,12 → 37,12 |
* Clear the error level. |
*/ |
cp0_status_write(cp0_status_read() & ~(cp0_status_bev_bootstrap_bit|cp0_status_erl_error_bit)); |
/* |
* Unmask hardware clock interrupt. |
*/ |
cp0_status_write(cp0_status_read() | (1<<cp0_status_im7_shift)); |
/* |
* Start hardware clock. |
*/ |
/SPARTAN/trunk/arch/mips/src/interrupt.c |
---|
35,26 → 35,26 |
pri_t cpu_priority_high(void) |
{ |
pri_t pri = (pri_t) cp0_status_read(); |
cp0_status_write(pri & ~cp0_status_ie_enabled_bit); |
return pri; |
pri_t pri = (pri_t) cp0_status_read(); |
cp0_status_write(pri & ~cp0_status_ie_enabled_bit); |
return pri; |
} |
pri_t cpu_priority_low(void) |
{ |
pri_t pri = (pri_t) cp0_status_read(); |
cp0_status_write(pri | cp0_status_ie_enabled_bit); |
return pri; |
pri_t pri = (pri_t) cp0_status_read(); |
cp0_status_write(pri | cp0_status_ie_enabled_bit); |
return pri; |
} |
void cpu_priority_restore(pri_t pri) |
{ |
cp0_status_write(cp0_status_read() | (pri & cp0_status_ie_enabled_bit)); |
cp0_status_write(cp0_status_read() | (pri & cp0_status_ie_enabled_bit)); |
} |
pri_t cpu_priority_read(void) |
{ |
return cp0_status_read(); |
return cp0_status_read(); |
} |
84,8 → 84,8 |
break; |
case 7: /* Timer Interrupt */ |
cp0_compare_write(cp0_compare_value); /* clear timer interrupt */ |
/* start counting over again */ |
cp0_count_write(0); |
/* start counting over again */ |
cp0_count_write(0); |
clock(); |
break; |
} |
/SPARTAN/trunk/arch/mips/src/start.S |
---|
51,16 → 51,16 |
cache_error_entry: |
j cache_error_handler |
nop |
.org 0x180 |
exception_entry: |
exception_handler: |
sub $29, STACK_SPACE |
REGISTERS_STORE $29 |
jal exception |
nop |
REGISTERS_LOAD $29 |
add $29, STACK_SPACE |
69,13 → 69,13 |
tlb_refill_handler: |
sub $29, STACK_SPACE |
REGISTERS_STORE $29 |
jal tlb_refill |
nop |
REGISTERS_LOAD $29 |
add $29, STACK_SPACE |
eret |
cache_error_handler: |
84,7 → 84,7 |
jal cache_error |
nop |
REGISTERS_LOAD $29 |
add $29, STACK_SPACE |
/SPARTAN/trunk/arch/mips/_link.ld |
---|
31,17 → 31,17 |
. = ABSOLUTE(hardcoded_ktext_size); |
.patch_1 : { |
LONG(ktext_end - ktext_start); |
LONG(ktext_end - ktext_start); |
} |
. = ABSOLUTE(hardcoded_kdata_size); |
.patch_2 : { |
LONG(kdata_end - kdata_start); |
LONG(kdata_end - kdata_start); |
} |
. = ABSOLUTE(hardcoded_load_address); |
.patch_3 : { |
LONG(0x80000000); |
LONG(0x80000000); |
} |
} |