| /SPARTAN/trunk/arch/mips/src/exception.c |
|---|
| 34,10 → 34,9 |
| #include <arch.h> |
| #include <debug.h> |
| void exception(void) |
| void exception(struct exception_regdump *pstate) |
| { |
| int excno; |
| __u32 epc; |
| __u32 epc_shift = 0; |
| ASSERT(CPU != NULL); |
| 45,18 → 44,14 |
| /* |
| * NOTE ON OPERATION ORDERING |
| * |
| * On entry, cpu_priority_high() must be called before exception bit is cleared. |
| * On exit, exception bit must be set before cpu_priority_restore() is called. |
| * On entry, cpu_priority_high() must be called before |
| * exception bit is cleared. |
| */ |
| cpu_priority_high(); |
| epc = cp0_epc_read(); |
| cp0_status_write(cp0_status_read() & ~ (cp0_status_exl_exception_bit | |
| cp0_status_um_bit)); |
| if (THREAD) { |
| THREAD->saved_epc = epc; |
| } |
| /* decode exception number and process the exception */ |
| switch (excno = (cp0_cause_read() >> 2) & 0x1f) { |
| case EXC_Int: |
| 64,7 → 59,7 |
| break; |
| case EXC_TLBL: |
| case EXC_TLBS: |
| tlb_invalid(); |
| tlb_invalid(pstate); |
| break; |
| case EXC_Mod: |
| panic("unhandled TLB Modification Exception\n"); |
| 114,12 → 109,5 |
| panic("unhandled exception %d\n", excno); |
| } |
| if (THREAD) |
| epc = THREAD->saved_epc; |
| /* Raise EXL bit before epc_write, so that we support |
| * properly nested exceptions |
| */ |
| cp0_status_write(cp0_status_read() | cp0_status_exl_exception_bit); |
| cp0_epc_write(epc + epc_shift); |
| pstate->epc += epc_shift; |
| } |
| /SPARTAN/trunk/arch/mips/src/context.S |
|---|
| 28,7 → 28,7 |
| #define __ASM__ |
| #include <arch/asm/regname.h> |
| #include "context_offset.h" |
| #include <arch/context_offset.h> |
| .text |
| /SPARTAN/trunk/arch/mips/src/mm/tlb.c |
|---|
| 35,22 → 35,22 |
| #include <symtab.h> |
| void tlb_refill(void) |
| void tlb_refill(struct exception_regdump *pstate) |
| { |
| panic("tlb_refill exception\n"); |
| } |
| void tlb_invalid(void) |
| void tlb_invalid(struct exception_regdump *pstate) |
| { |
| char *symbol = ""; |
| if (THREAD) { |
| char *s = get_symtab_entry(THREAD->saved_epc); |
| char *s = get_symtab_entry(pstate->epc); |
| if (s) |
| symbol = s; |
| } |
| panic("%X: TLB exception at %X(%s)\n", cp0_badvaddr_read(), |
| THREAD ? THREAD->saved_epc : 0, symbol); |
| pstate->epc, symbol); |
| } |
| void tlb_invalidate(int asid) |
| /SPARTAN/trunk/arch/mips/src/start.S |
|---|
| 31,7 → 31,7 |
| #include <arch/asm/regname.h> |
| #include <arch/mm/page.h> |
| #include <arch/asm/boot.h> |
| #include <arch/context.h> |
| #include <arch/context_offset.h> |
| .text |
| 55,7 → 55,7 |
| sw $a1,EOFFSET_A1(\r) |
| sw $a2,EOFFSET_A2(\r) |
| sw $a3,EOFFSET_A3(\r) |
| sw $t0,EOFFSET_A4(\r) |
| sw $t0,EOFFSET_T0(\r) |
| sw $t1,EOFFSET_T1(\r) |
| sw $t2,EOFFSET_T2(\r) |
| sw $t3,EOFFSET_T3(\r) |
| 86,6 → 86,8 |
| mfc0 $at, $status |
| sw $at,EOFFSET_STATUS(\r) |
| mfc0 $at, $epc |
| sw $at,EOFFSET_EPC(\r) |
| .endm |
| .macro REGISTERS_LOAD r |
| 95,7 → 97,7 |
| lw $a1,EOFFSET_A1(\r) |
| lw $a2,EOFFSET_A2(\r) |
| lw $a3,EOFFSET_A3(\r) |
| lw $t0,EOFFSET_A4(\r) |
| lw $t0,EOFFSET_T0(\r) |
| lw $t1,EOFFSET_T1(\r) |
| lw $t2,EOFFSET_T2(\r) |
| lw $t3,EOFFSET_T3(\r) |
| 124,6 → 126,8 |
| lw $at,EOFFSET_STATUS(\r) |
| mtc0 $at, $status |
| lw $at,EOFFSET_EPC(\r) |
| mtc0 $at, $epc |
| lw $at,EOFFSET_AT(\r) |
| lw $sp,EOFFSET_SP(\r) |
| 191,7 → 195,8 |
| REGISTERS_STORE $k0 |
| add $sp, $k0, 0 |
| jal exception |
| add $a0, $sp, 0 |
| jal exception /* exception(register_space) */ |
| nop |
| REGISTERS_LOAD $sp |
| 205,7 → 210,8 |
| REGISTERS_STORE $k0 |
| add $sp, $k0, 0 |
| jal tlb_refill |
| add $a0, $sp, 0 |
| jal tlb_refill /* tlb_refill(register_space) */ |
| nop |
| REGISTERS_LOAD $sp |