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Ignore whitespace Rev 124 → Rev 125

/SPARTAN/trunk/arch/mips/src/cpu/cpu.c
39,42 → 39,42
char *vendor;
char *model;
} imp_data[] = {
{ "Invalid", "Invalid" }, /* 0x00 */
{ "MIPS", "R2000" }, /* 0x01 */
{ "MIPS", "R3000" }, /* 0x02 */
{ "MIPS", "R6000" }, /* 0x03 */
{ "MIPS", " R4000/R4400" }, /* 0x04 */
{ "LSI Logic", "R3000" }, /* 0x05 */
{ "MIPS", "R6000A" }, /* 0x06 */
{ "IDT", "3051/3052" }, /* 0x07 */
{ "Invalid", "Invalid" }, /* 0x08 */
{ "MIPS", "R10000/T5" }, /* 0x09 */
{ "MIPS", "R4200" }, /* 0x0a */
{ "Unknown", "Unknown" }, /* 0x0b */
{ "Unknown", "Unknown" }, /* 0x0c */
{ "Invalid", "Invalid" }, /* 0x0d */
{ "Invalid", "Invalid" }, /* 0x0e */
{ "Invalid", "Invalid" }, /* 0x0f */
{ "MIPS", "R8000" }, /* 0x10 */
{ "Invalid", "Invalid" }, /* 0x11 */
{ "Invalid", "Invalid" }, /* 0x12 */
{ "Invalid", "Invalid" }, /* 0x13 */
{ "Invalid", "Invalid" }, /* 0x14 */
{ "Invalid", "Invalid" }, /* 0x15 */
{ "Invalid", "Invalid" }, /* 0x16 */
{ "Invalid", "Invalid" }, /* 0x17 */
{ "Invalid", "Invalid" }, /* 0x18 */
{ "Invalid", "Invalid" }, /* 0x19 */
{ "Invalid", "Invalid" }, /* 0x1a */
{ "Invalid", "Invalid" }, /* 0x1b */
{ "Invalid", "Invalid" }, /* 0x1c */
{ "Invalid", "Invalid" }, /* 0x1d */
{ "Invalid", "Invalid" }, /* 0x1e */
{ "Invalid", "Invalid" }, /* 0x1f */
{ "QED", "R4600" }, /* 0x20 */
{ "Sony", "R3000" }, /* 0x21 */
{ "Toshiba", "R3000" }, /* 0x22 */
{ "NKK", "R3000" } /* 0x23 */
{ "Invalid", "Invalid" }, /* 0x00 */
{ "MIPS", "R2000" }, /* 0x01 */
{ "MIPS", "R3000" }, /* 0x02 */
{ "MIPS", "R6000" }, /* 0x03 */
{ "MIPS", " R4000/R4400" }, /* 0x04 */
{ "LSI Logic", "R3000" }, /* 0x05 */
{ "MIPS", "R6000A" }, /* 0x06 */
{ "IDT", "3051/3052" }, /* 0x07 */
{ "Invalid", "Invalid" }, /* 0x08 */
{ "MIPS", "R10000/T5" }, /* 0x09 */
{ "MIPS", "R4200" }, /* 0x0a */
{ "Unknown", "Unknown" }, /* 0x0b */
{ "Unknown", "Unknown" }, /* 0x0c */
{ "Invalid", "Invalid" }, /* 0x0d */
{ "Invalid", "Invalid" }, /* 0x0e */
{ "Invalid", "Invalid" }, /* 0x0f */
{ "MIPS", "R8000" }, /* 0x10 */
{ "Invalid", "Invalid" }, /* 0x11 */
{ "Invalid", "Invalid" }, /* 0x12 */
{ "Invalid", "Invalid" }, /* 0x13 */
{ "Invalid", "Invalid" }, /* 0x14 */
{ "Invalid", "Invalid" }, /* 0x15 */
{ "Invalid", "Invalid" }, /* 0x16 */
{ "Invalid", "Invalid" }, /* 0x17 */
{ "Invalid", "Invalid" }, /* 0x18 */
{ "Invalid", "Invalid" }, /* 0x19 */
{ "Invalid", "Invalid" }, /* 0x1a */
{ "Invalid", "Invalid" }, /* 0x1b */
{ "Invalid", "Invalid" }, /* 0x1c */
{ "Invalid", "Invalid" }, /* 0x1d */
{ "Invalid", "Invalid" }, /* 0x1e */
{ "Invalid", "Invalid" }, /* 0x1f */
{ "QED", "R4600" }, /* 0x20 */
{ "Sony", "R3000" }, /* 0x21 */
{ "Toshiba", "R3000" }, /* 0x22 */
{ "NKK", "R3000" } /* 0x23 */
};
 
void cpu_arch_init(void)
/SPARTAN/trunk/arch/mips/src/mips.c
37,12 → 37,12
* Clear the error level.
*/
cp0_status_write(cp0_status_read() & ~(cp0_status_bev_bootstrap_bit|cp0_status_erl_error_bit));
 
/*
* Unmask hardware clock interrupt.
*/
cp0_status_write(cp0_status_read() | (1<<cp0_status_im7_shift));
 
/*
* Start hardware clock.
*/
/SPARTAN/trunk/arch/mips/src/interrupt.c
35,26 → 35,26
 
pri_t cpu_priority_high(void)
{
pri_t pri = (pri_t) cp0_status_read();
cp0_status_write(pri & ~cp0_status_ie_enabled_bit);
return pri;
pri_t pri = (pri_t) cp0_status_read();
cp0_status_write(pri & ~cp0_status_ie_enabled_bit);
return pri;
}
 
pri_t cpu_priority_low(void)
{
pri_t pri = (pri_t) cp0_status_read();
cp0_status_write(pri | cp0_status_ie_enabled_bit);
return pri;
pri_t pri = (pri_t) cp0_status_read();
cp0_status_write(pri | cp0_status_ie_enabled_bit);
return pri;
}
 
void cpu_priority_restore(pri_t pri)
{
cp0_status_write(cp0_status_read() | (pri & cp0_status_ie_enabled_bit));
cp0_status_write(cp0_status_read() | (pri & cp0_status_ie_enabled_bit));
}
 
pri_t cpu_priority_read(void)
{
return cp0_status_read();
return cp0_status_read();
}
 
 
84,8 → 84,8
break;
case 7: /* Timer Interrupt */
cp0_compare_write(cp0_compare_value); /* clear timer interrupt */
/* start counting over again */
cp0_count_write(0);
/* start counting over again */
cp0_count_write(0);
clock();
break;
}
/SPARTAN/trunk/arch/mips/src/start.S
51,16 → 51,16
cache_error_entry:
j cache_error_handler
nop
 
.org 0x180
exception_entry:
exception_handler:
sub $29, STACK_SPACE
REGISTERS_STORE $29
 
jal exception
nop
 
REGISTERS_LOAD $29
add $29, STACK_SPACE
 
69,13 → 69,13
tlb_refill_handler:
sub $29, STACK_SPACE
REGISTERS_STORE $29
 
jal tlb_refill
nop
 
REGISTERS_LOAD $29
add $29, STACK_SPACE
 
eret
 
cache_error_handler:
84,7 → 84,7
 
jal cache_error
nop
 
REGISTERS_LOAD $29
add $29, STACK_SPACE