| /SPARTAN/trunk/arch/mips/include/asm/boot.h |
|---|
| 34,7 → 34,7 |
| #define TEMP_STACK_SIZE 0x100 |
| /* Kernel startup address */ |
| #define KERNEL_STARTUP_ADDRESS 0x80000300 |
| #define KERNEL_LOAD_ADDRESS 0x80100000 |
| #endif |
| /SPARTAN/trunk/arch/mips/include/exception.h |
|---|
| 91,5 → 91,7 |
| }; |
| extern void exception(struct exception_regdump *pstate); |
| extern void tlb_refill_entry(void); |
| extern void exception_entry(void); |
| extern void cache_error_entry(void); |
| #endif |
| /SPARTAN/trunk/arch/mips/include/fpu_context.h |
|---|
| 32,10 → 32,8 |
| #include <arch/types.h> |
| struct fpu_context { |
| /* TODO: define MIPS FPU context */ |
| __native dregs[32]; |
| __native cregs[32]; |
| }; |
| #endif |
| /SPARTAN/trunk/arch/mips/include/byteorder.h |
|---|
| 30,6 → 30,16 |
| #define __mips_BYTEORDER_H__ |
| /* MIPS is little-endian */ |
| #define native_le2host(n) n |
| #ifdef BIG_ENDIAN |
| static inline __native native_le2host(__native n) |
| { |
| return ((n & 0xff) << 24) | |
| ((n & 0xff00) << 8) | |
| ((n & 0xff0000) >> 8) | |
| ((n & 0xff000000) >> 24); |
| } |
| #else |
| # define native_le2host(n) n |
| #endif |
| #endif |
| /SPARTAN/trunk/arch/mips/include/thread.h |
|---|
| 29,6 → 29,8 |
| #ifndef __mips_THREAD_H__ |
| #define __mips_THREAD_H__ |
| #define ARCH_THREAD_DATA |
| #include <arch/exception.h> |
| #define ARCH_THREAD_DATA struct exception_regdump *pstate |
| #endif |
| /SPARTAN/trunk/arch/mips/include/asm.h |
|---|
| 33,8 → 33,13 |
| #include <typedefs.h> |
| #include <config.h> |
| #define cpu_sleep() ; |
| static inline void cpu_sleep(void) |
| { |
| /* Most of the simulators do not support */ |
| /* __asm__ volatile ("wait"); */ |
| } |
| /** Return base address of current stack |
| * |
| * Return the base address of the current stack. |
| /SPARTAN/trunk/arch/mips/include/cp0.h |
|---|
| 34,8 → 34,9 |
| #define cp0_status_ie_enabled_bit (1<<0) |
| #define cp0_status_exl_exception_bit (1<<1) |
| #define cp0_status_erl_error_bit (1<<2) |
| #define cp0_status_um_bit (1<<4) |
| #define cp0_status_bev_bootstrap_bit (1<<22) |
| #define cp0_status_um_bit (1<<4) |
| #define cp0_status_fpu_bit (1<<29) |
| #define cp0_status_im7_shift 15 |
| /* |
| 44,6 → 45,26 |
| */ |
| #define cp0_compare_value 10000 |
| static inline void tlbp(void) |
| { |
| __asm__ volatile ("tlbp"); |
| } |
| static inline void tlbr(void) |
| { |
| __asm__ volatile ("tlbr"); |
| } |
| static inline void tlbwi(void) |
| { |
| __asm__ volatile ("tlbwi"); |
| } |
| static inline void tlbwr(void) |
| { |
| __asm__ volatile ("tlbwr"); |
| } |
| extern __u32 cp0_index_read(void); |
| extern void cp0_idnex_write(__u32 val); |
| 86,9 → 107,4 |
| extern __u32 cp0_prid_read(void); |
| extern void tlbp(void); |
| extern void tlbr(void); |
| extern void tlbwi(void); |
| extern void tlbwr(void); |
| #endif |