/SPARTAN/trunk/arch/mips/include/cp0.h |
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41,6 → 41,11 |
#define cp0_status_im_shift 8 |
#define cp0_status_im_mask 0xff00 |
#define cp0_cause_excno(cause) ((cause >> 2) & 0x1f) |
#define cp0_cause_coperr(cause) ((cause >> 28) & 0x3) |
#define fpu_cop_id 1 |
/* |
* Magic value for use in msim. |
* On AMD Duron 800Mhz, this roughly seems like one us. |