| /SPARTAN/trunk/arch/mips/include/asm/boot.h |
|---|
| 33,8 → 33,4 |
| /* Temporary stack size for boot process */ |
| #define TEMP_STACK_SIZE 0x100 |
| /* Kernel startup address */ |
| #define KERNEL_LOAD_ADDRESS 0x80100000 |
| #endif |
| /SPARTAN/trunk/arch/mips/include/interrupt.h |
|---|
| 29,6 → 29,8 |
| #ifndef __INTERRUPT_H__ |
| #define __INTERRUPT_H__ |
| #define TIMER_INTERRUPT 7 |
| extern void interrupt(void); |
| #endif |
| /SPARTAN/trunk/arch/mips/include/console.h |
|---|
| 38,4 → 38,7 |
| void console_init(void); |
| extern int bios_write(int fd, const char *buf, int size, int *cnt); |
| #endif |
| /SPARTAN/trunk/arch/mips/include/cp0.h |
|---|
| 38,7 → 38,9 |
| #define cp0_status_bev_bootstrap_bit (1<<22) |
| #define cp0_status_fpu_bit (1<<29) |
| #define cp0_status_im7_shift 15 |
| #define cp0_status_im_shift 8 |
| #define cp0_status_im_mask 0xff00 |
| /* |
| * Magic value for use in msim. |
| * On AMD Duron 800Mhz, this roughly seems like one us. |
| 63,6 → 65,10 |
| __asm__ volatile ("tlbwr"); |
| } |
| #define cp0_mask_all_int() cp0_status_write(cp0_status_read() & ~(cp0_status_im_mask)) |
| #define cp0_unmask_all_int() cp0_status_write(cp0_status_read() | cp0_status_im_mask) |
| #define cp0_mask_int(it) cp0_status_write(cp0_status_read() & ~(1<<(cp0_status_im_shift+(it)))) |
| #define cp0_unmask_int(it) cp0_status_write(cp0_status_read() | (1<<(cp0_status_im_shift+(it)))) |
| extern __u32 cp0_index_read(void); |
| /SPARTAN/trunk/arch/mips/include/mm/memory_init.h |
|---|
| 32,5 → 32,6 |
| #include <config.h> |
| #define get_memory_size() CONFIG_MEMORY_SIZE |
| //#define get_memory_size() 150*1024*1024 |
| #endif |