/SPARTAN/trunk/arch/mips/_link.ld |
---|
File deleted |
/SPARTAN/trunk/arch/mips/_link.ld.in |
---|
0,0 → 1,57 |
/* |
* MIPS linker script |
* |
* kernel text |
* kernel data |
* |
*/ |
#undef mips |
#define mips mips |
OUTPUT_FORMAT(BFD) |
OUTPUT_ARCH(mips) |
ENTRY(kernel_image_start) |
SECTIONS { |
. = 0x80100000; |
.text : { |
ktext_start = .; |
*(.text); |
ktext_end = .; |
} |
.data : { |
kdata_start = .; |
*(.data); /* initialized data */ |
hardcoded_ktext_size = .; |
LONG(ktext_end - ktext_start); |
hardcoded_kdata_size = .; |
LONG(kdata_end - kdata_start); |
hardcoded_load_address = .; |
LONG(0x80100000); |
} |
_gp = . + 0x8000; |
.lit8 : { *(.lit8) } |
.lit4 : { *(.lit4) } |
.sdata : { *(.sdata) } |
.sbss : { |
*(.sbss); |
*(.scommon); |
} |
.bss : { |
*(.bss); /* uninitialized static variables */ |
*(COMMON); /* global variables */ |
} |
mysymtable : { |
symbol_table = .; |
*(symtab.*); /* Symbol table, must be LAST symbol!*/ |
} |
kdata_end = .; |
.mdebug : { *(.mdebug) } |
.stab 0 : { *(.stab) } |
.stabstr 0 : { *(.stabstr) } |
.comment : { *(.comment) } |
.note : { *(.note) } |
} |
/SPARTAN/trunk/arch/mips/boot/boot.S |
---|
36,8 → 36,8 |
.global start |
start: |
lui $ra, KERNEL_STARTUP_ADDRESS >> 16 |
ori $ra, KERNEL_STARTUP_ADDRESS & 0xffff |
lui $ra, KERNEL_LOAD_ADDRESS >> 16 |
ori $ra, KERNEL_LOAD_ADDRESS & 0xffff |
j $ra |
nop |
/SPARTAN/trunk/arch/mips/include/asm/boot.h |
---|
34,7 → 34,7 |
#define TEMP_STACK_SIZE 0x100 |
/* Kernel startup address */ |
#define KERNEL_STARTUP_ADDRESS 0x80000300 |
#define KERNEL_LOAD_ADDRESS 0x80100000 |
#endif |
/SPARTAN/trunk/arch/mips/include/exception.h |
---|
91,5 → 91,7 |
}; |
extern void exception(struct exception_regdump *pstate); |
extern void tlb_refill_entry(void); |
extern void exception_entry(void); |
extern void cache_error_entry(void); |
#endif |
/SPARTAN/trunk/arch/mips/include/fpu_context.h |
---|
32,10 → 32,8 |
#include <arch/types.h> |
struct fpu_context { |
/* TODO: define MIPS FPU context */ |
__native dregs[32]; |
__native cregs[32]; |
}; |
#endif |
/SPARTAN/trunk/arch/mips/include/byteorder.h |
---|
30,6 → 30,16 |
#define __mips_BYTEORDER_H__ |
/* MIPS is little-endian */ |
#define native_le2host(n) n |
#ifdef BIG_ENDIAN |
static inline __native native_le2host(__native n) |
{ |
return ((n & 0xff) << 24) | |
((n & 0xff00) << 8) | |
((n & 0xff0000) >> 8) | |
((n & 0xff000000) >> 24); |
} |
#else |
# define native_le2host(n) n |
#endif |
#endif |
/SPARTAN/trunk/arch/mips/include/thread.h |
---|
29,6 → 29,8 |
#ifndef __mips_THREAD_H__ |
#define __mips_THREAD_H__ |
#define ARCH_THREAD_DATA |
#include <arch/exception.h> |
#define ARCH_THREAD_DATA struct exception_regdump *pstate |
#endif |
/SPARTAN/trunk/arch/mips/include/asm.h |
---|
33,8 → 33,13 |
#include <typedefs.h> |
#include <config.h> |
#define cpu_sleep() ; |
static inline void cpu_sleep(void) |
{ |
/* Most of the simulators do not support */ |
/* __asm__ volatile ("wait"); */ |
} |
/** Return base address of current stack |
* |
* Return the base address of the current stack. |
/SPARTAN/trunk/arch/mips/include/cp0.h |
---|
34,8 → 34,9 |
#define cp0_status_ie_enabled_bit (1<<0) |
#define cp0_status_exl_exception_bit (1<<1) |
#define cp0_status_erl_error_bit (1<<2) |
#define cp0_status_um_bit (1<<4) |
#define cp0_status_bev_bootstrap_bit (1<<22) |
#define cp0_status_um_bit (1<<4) |
#define cp0_status_fpu_bit (1<<29) |
#define cp0_status_im7_shift 15 |
/* |
44,6 → 45,26 |
*/ |
#define cp0_compare_value 10000 |
static inline void tlbp(void) |
{ |
__asm__ volatile ("tlbp"); |
} |
static inline void tlbr(void) |
{ |
__asm__ volatile ("tlbr"); |
} |
static inline void tlbwi(void) |
{ |
__asm__ volatile ("tlbwi"); |
} |
static inline void tlbwr(void) |
{ |
__asm__ volatile ("tlbwr"); |
} |
extern __u32 cp0_index_read(void); |
extern void cp0_idnex_write(__u32 val); |
86,9 → 107,4 |
extern __u32 cp0_prid_read(void); |
extern void tlbp(void); |
extern void tlbr(void); |
extern void tlbwi(void); |
extern void tlbwr(void); |
#endif |
/SPARTAN/trunk/arch/mips/Makefile.inc |
---|
13,11 → 13,42 |
ASFLAGS=-mips3 |
DEFS=-DARCH=$(ARCH) |
CPPFLAGS=$(DEFS) -mno-abicalls -nostdinc -I../include |
CFLAGS=$(CPPFLAGS) -mips2 -G 0 -nostdlib -fno-builtin -Werror-implicit-function-declaration -Wmissing-prototypes -Werror -O2 -msoft-float |
DEFS=-DARCH=$(ARCH) -DMACHINE=${MACHINE} |
CFLAGS=$(DEFS) -mno-abicalls -mips3 -G 0 -nostdlib -fno-builtin -O2 |
LFLAGS=-mips2 -M -no-check-sections |
# It seems that on big endian either GCC or the simulators |
# have the swl/swr/lwl/lwr instructions wrong. Just for sure, |
# disable it with -mmemcpy (force calling memcpy instead of inlining) |
ifeq (${MACHINE},indy) |
CFLAGS += -EB -mmemcpy -DBIG_ENDIAN -DHAVE_FPU -DFPU_LAZY |
BFD = elf32-big |
endif |
ifeq (${MACHINE},lgxemul) |
CFLAGS += -DHAVE_FPU -DFPU_LAZY |
BFD = ecoff-littlemips |
endif |
ifeq (${MACHINE},bgxemul) |
CFLAGS += -EB -mmemcpy -DBIG_ENDIAN -DHAVE_FPU -DFPU_LAZY |
BFD = ecoff-bigmips |
endif |
ifeq (${MACHINE},msim) |
BFD = binary |
CFLAGS += -msoft-float |
endif |
ifeq (${MACHINE},simics) |
BFD = elf32-little |
CFLAGS += -msoft-float |
endif |
../arch/$(ARCH)/_link.ld: ../arch/$(ARCH)/_link.ld.in |
$(CC) $(CFLAGS) -C -DBFD=${BFD} -E -x c $< | grep -v "^\#" > $@ |
arch_sources= \ |
arch/start.S \ |
arch/context.S \ |
/SPARTAN/trunk/arch/mips/src/exception.c |
---|
51,6 → 51,9 |
cpu_priority_high(); |
cp0_status_write(cp0_status_read() & ~ (cp0_status_exl_exception_bit | |
cp0_status_um_bit)); |
/* Save pstate so that the threads can access it */ |
if (THREAD) |
THREAD->pstate = pstate; |
/* decode exception number and process the exception */ |
switch (excno = (cp0_cause_read() >> 2) & 0x1f) { |
85,7 → 88,11 |
panic("unhandled Reserved Instruction Exception\n"); |
break; |
case EXC_CpU: |
#ifdef FPU_LAZY |
scheduler_fpu_lazy_request(); |
#else |
panic("unhandled Coprocessor Unusable Exception\n"); |
#endif |
break; |
case EXC_Ov: |
panic("unhandled Arithmetic Overflow Exception\n"); |
110,4 → 117,8 |
} |
pstate->epc += epc_shift; |
/* Probable not needed, but just for sure that nobody |
* will continue accessing it */ |
if (THREAD) |
THREAD->pstate = NULL; |
} |
/SPARTAN/trunk/arch/mips/src/fpu_context.c |
---|
28,13 → 28,28 |
*/ |
#include <fpu_context.h> |
#include <arch.h> |
#include <arch/cp0.h> |
void fpu_context_save(fpu_context_t *fctx) |
void fpu_disable(void) |
{ |
#ifdef HAVE_FPU |
cp0_status_write(cp0_status_read() & ~cp0_status_fpu_bit); |
if (THREAD && THREAD->pstate) |
THREAD->pstate->status &= ~cp0_status_fpu_bit; |
#endif |
} |
void fpu_enable(void) |
{ |
#ifdef HAVE_FPU |
cp0_status_write(cp0_status_read() | cp0_status_fpu_bit); |
if (THREAD && THREAD->pstate) |
THREAD->pstate->status |= cp0_status_fpu_bit; |
#endif |
} |
void fpu_context_restore(fpu_context_t *fctx) |
void fpu_init(void) |
{ |
/* TODO: Zero all registers */ |
} |
/SPARTAN/trunk/arch/mips/src/asm.S |
---|
26,6 → 26,8 |
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
# |
#include <arch/asm/regname.h> |
.text |
.macro cp0_read reg |
115,30 → 117,6 |
cp0_prid_read: cp0_read $15 |
.global tlbp |
tlbp: |
tlbp |
j $31 |
nop |
.global tlbr |
tlbr: |
tlbr |
j $31 |
nop |
.global tlbwi |
tlbwi: |
tlbwi |
j $31 |
nop |
.global tlbwr |
tlbwr: |
tlbwr |
j $31 |
nop |
.global cpu_halt |
cpu_halt: |
j cpu_halt |
155,6 → 133,169 |
j _memcpy |
nop |
.macro fpu_gp_save reg ctx |
mfc1 $t0,$\reg |
sw $t0, \reg*4(\ctx) |
.endm |
.macro fpu_gp_restore reg ctx |
lw $t0, \reg*4(\ctx) |
mtc1 $t0,$\reg |
.endm |
.macro fpu_ct_save reg ctx |
cfc1 $t0,$1 |
sw $t0, (\reg+32)*4(\ctx) |
.endm |
.macro fpu_ct_restore reg ctx |
lw $t0, (\reg+32)*4(\ctx) |
ctc1 $t0,$\reg |
.endm |
.global fpu_context_save |
fpu_context_save: |
#ifdef HAVE_FPU |
fpu_gp_save 0,$a0 |
fpu_gp_save 1,$a0 |
fpu_gp_save 2,$a0 |
fpu_gp_save 3,$a0 |
fpu_gp_save 4,$a0 |
fpu_gp_save 5,$a0 |
fpu_gp_save 6,$a0 |
fpu_gp_save 7,$a0 |
fpu_gp_save 8,$a0 |
fpu_gp_save 9,$a0 |
fpu_gp_save 10,$a0 |
fpu_gp_save 11,$a0 |
fpu_gp_save 12,$a0 |
fpu_gp_save 13,$a0 |
fpu_gp_save 14,$a0 |
fpu_gp_save 15,$a0 |
fpu_gp_save 16,$a0 |
fpu_gp_save 17,$a0 |
fpu_gp_save 18,$a0 |
fpu_gp_save 19,$a0 |
fpu_gp_save 20,$a0 |
fpu_gp_save 21,$a0 |
fpu_gp_save 22,$a0 |
fpu_gp_save 23,$a0 |
fpu_gp_save 24,$a0 |
fpu_gp_save 25,$a0 |
fpu_gp_save 26,$a0 |
fpu_gp_save 27,$a0 |
fpu_gp_save 28,$a0 |
fpu_gp_save 29,$a0 |
fpu_gp_save 30,$a0 |
fpu_gp_save 31,$a0 |
fpu_ct_save 1,$a0 |
fpu_ct_save 2,$a0 |
fpu_ct_save 3,$a0 |
fpu_ct_save 4,$a0 |
fpu_ct_save 5,$a0 |
fpu_ct_save 6,$a0 |
fpu_ct_save 7,$a0 |
fpu_ct_save 8,$a0 |
fpu_ct_save 9,$a0 |
fpu_ct_save 10,$a0 |
fpu_ct_save 11,$a0 |
fpu_ct_save 12,$a0 |
fpu_ct_save 13,$a0 |
fpu_ct_save 14,$a0 |
fpu_ct_save 15,$a0 |
fpu_ct_save 16,$a0 |
fpu_ct_save 17,$a0 |
fpu_ct_save 18,$a0 |
fpu_ct_save 19,$a0 |
fpu_ct_save 20,$a0 |
fpu_ct_save 21,$a0 |
fpu_ct_save 22,$a0 |
fpu_ct_save 23,$a0 |
fpu_ct_save 24,$a0 |
fpu_ct_save 25,$a0 |
fpu_ct_save 26,$a0 |
fpu_ct_save 27,$a0 |
fpu_ct_save 28,$a0 |
fpu_ct_save 29,$a0 |
fpu_ct_save 30,$a0 |
fpu_ct_save 31,$a0 |
#endif |
j $ra |
nop |
.global fpu_context_restore |
fpu_context_restore: |
#ifdef HAVE_FPU |
fpu_gp_restore 0,$a0 |
fpu_gp_restore 1,$a0 |
fpu_gp_restore 2,$a0 |
fpu_gp_restore 3,$a0 |
fpu_gp_restore 4,$a0 |
fpu_gp_restore 5,$a0 |
fpu_gp_restore 6,$a0 |
fpu_gp_restore 7,$a0 |
fpu_gp_restore 8,$a0 |
fpu_gp_restore 9,$a0 |
fpu_gp_restore 10,$a0 |
fpu_gp_restore 11,$a0 |
fpu_gp_restore 12,$a0 |
fpu_gp_restore 13,$a0 |
fpu_gp_restore 14,$a0 |
fpu_gp_restore 15,$a0 |
fpu_gp_restore 16,$a0 |
fpu_gp_restore 17,$a0 |
fpu_gp_restore 18,$a0 |
fpu_gp_restore 19,$a0 |
fpu_gp_restore 20,$a0 |
fpu_gp_restore 21,$a0 |
fpu_gp_restore 22,$a0 |
fpu_gp_restore 23,$a0 |
fpu_gp_restore 24,$a0 |
fpu_gp_restore 25,$a0 |
fpu_gp_restore 26,$a0 |
fpu_gp_restore 27,$a0 |
fpu_gp_restore 28,$a0 |
fpu_gp_restore 29,$a0 |
fpu_gp_restore 30,$a0 |
fpu_gp_restore 31,$a0 |
fpu_ct_restore 1,$a0 |
fpu_ct_restore 2,$a0 |
fpu_ct_restore 3,$a0 |
fpu_ct_restore 4,$a0 |
fpu_ct_restore 5,$a0 |
fpu_ct_restore 6,$a0 |
fpu_ct_restore 7,$a0 |
fpu_ct_restore 8,$a0 |
fpu_ct_restore 9,$a0 |
fpu_ct_restore 10,$a0 |
fpu_ct_restore 11,$a0 |
fpu_ct_restore 12,$a0 |
fpu_ct_restore 13,$a0 |
fpu_ct_restore 14,$a0 |
fpu_ct_restore 15,$a0 |
fpu_ct_restore 16,$a0 |
fpu_ct_restore 17,$a0 |
fpu_ct_restore 18,$a0 |
fpu_ct_restore 19,$a0 |
fpu_ct_restore 20,$a0 |
fpu_ct_restore 21,$a0 |
fpu_ct_restore 22,$a0 |
fpu_ct_restore 23,$a0 |
fpu_ct_restore 24,$a0 |
fpu_ct_restore 25,$a0 |
fpu_ct_restore 26,$a0 |
fpu_ct_restore 27,$a0 |
fpu_ct_restore 28,$a0 |
fpu_ct_restore 29,$a0 |
fpu_ct_restore 30,$a0 |
fpu_ct_restore 31,$a0 |
#endif |
j $ra |
nop |
# THIS IS USERSPACE CODE |
.global utext |
utext: |
/SPARTAN/trunk/arch/mips/src/console.c |
---|
31,8 → 31,6 |
#include <arch/cp0.h> |
#include <arch/console.h> |
static void (*putchar_func)(const char ch) = NULL; |
static void cons_putchar(const char ch) |
{ |
*((char *) VIDEORAM) = ch; |
52,6 → 50,8 |
*(SERIAL_PORT_BASE) = ch; |
} |
static void (*putchar_func)(const char ch) = cons_putchar; |
void console_init(void) |
{ |
/* The LSR on the start usually contains this value */ |
/SPARTAN/trunk/arch/mips/src/mips.c |
---|
34,9 → 34,27 |
#include <mm/vm.h> |
#include <userspace.h> |
#include <arch/console.h> |
#include <memstr.h> |
/* Size of the code jumping to the exception handler code |
* - J+NOP |
*/ |
#define EXCEPTION_JUMP_SIZE 8 |
#define TLB_EXC ((char *) 0x80000000) |
#define NORM_EXC ((char *) 0x80000180) |
#define CACHE_EXC ((char *) 0x80000100) |
#include <arch/debug.h> |
void arch_pre_mm_init(void) |
{ |
/* Copy the exception vectors to the right places */ |
memcpy(TLB_EXC, (char *)tlb_refill_entry, EXCEPTION_JUMP_SIZE); |
memcpy(NORM_EXC, (char *)exception_entry, EXCEPTION_JUMP_SIZE); |
memcpy(CACHE_EXC, (char *)cache_error_entry, EXCEPTION_JUMP_SIZE); |
/* |
* Switch to BEV normal level so that exception vectors point to the kernel. |
* Clear the error level. |
/SPARTAN/trunk/arch/mips/src/mm/frame.c |
---|
31,4 → 31,6 |
void frame_arch_init(void) |
{ |
/* Disable first megabyte (God knows why) */ |
frame_region_not_free(0, 1024*1024); |
} |
/SPARTAN/trunk/arch/mips/src/panic.S |
---|
32,11 → 32,12 |
.set noreorder |
.set nomacro |
#include <arch/asm/regname.h> |
.global panic_printf |
/* From printf return directly to halt() */ |
panic_printf: |
jal printf |
nop |
j cpu_halt |
nop |
lui $ra, %hi(halt) |
j printf |
ori $ra, %lo(halt) |
/SPARTAN/trunk/arch/mips/src/dummy.S |
---|
32,15 → 32,9 |
.global calibrate_delay_loop |
.global asm_delay_loop |
.global dummy |
.global fpu_enable |
.global fpu_disable |
.global fpu_init |
calibrate_delay_loop: |
asm_delay_loop: |
fpu_enable: |
fpu_disable: |
fpu_init: |
dummy: |
j $31 |
/SPARTAN/trunk/arch/mips/src/start.S |
---|
153,26 → 153,6 |
.endm |
.org 0x0 |
tlb_refill_entry: |
j tlb_refill_handler |
nop |
.org 0x100 |
cache_error_entry: |
j cache_error_handler |
nop |
.org 0x180 |
norm_exception: |
j exception_handler |
nop |
.org 0x200 |
iv_exception: |
j exception_handler |
nop |
.org KA2PA(KERNEL_STARTUP_ADDRESS) |
kernel_image_start: |
/* Load temporary stack */ |
lui $sp, %hi(end_stack) |
186,10 → 166,23 |
.space TEMP_STACK_SIZE |
end_stack: |
end_stack: |
tlb_refill_entry: |
j tlb_refill_handler |
nop |
cache_error_entry: |
j cache_error_handler |
nop |
exception_entry: |
j exception_handler |
nop |
exception_handler: |
exception_entry: |
KERNEL_STACK_TO_K0 |
sub $k0, REGISTER_SPACE |
REGISTERS_STORE $k0 |