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• This comparison shows the changes necessary to convert path

  → /SPARTAN/trunk/arch/ia64/ @ 469

  → /SPARTAN/trunk/arch/ia64/ @ 470

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• Compare Path:	Rev

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Ignore whitespace Rev 469 → Rev 470

/SPARTAN/trunk/arch/ia64/include/interrupt.h
29,11 → 29,34
#ifndef __ia64_INTERRUPT_H__
#define __ia64_INTERRUPT_H__
#include <arch/types.h>
/** External interrupt vectors. */
#define INTERRUPT_TIMER 0
#define INTERRUPT_SPURIOUS 15
#define EOI 0 /**< The actual value doesn't matter. */
extern void external_interrupt(void);
struct exception_regdump {
__address ar_bsp;
__address ar_bspstore;
__u64 ar_rnat;
__u64 ar_ifs;
__u64 ar_pfs;
__u64 ar_rsc;
__address cr_ifa;
__u64 cr_isr;
__address cr_iipa;
__u64 cr_ips;
__address cr_iip;
__u64 pr;
} __attribute__ ((packed));
extern void *ivt;
extern void general_exception(__u64 vector, struct exception_regdump *pstate);
extern void break_instruction(__u64 vector, struct exception_regdump *pstate);
extern void universal_handler(__u64 vector, struct exception_regdump *pstate);
extern void external_interrupt(__u64 vector, struct exception_regdump *pstate);
#endif

/SPARTAN/trunk/arch/ia64/include/asm.h
48,6 → 48,29
return v;
}
/** Read IVA (Interruption Vector Address).
*
* @return Return location of interruption vector table.
*/
static inline __u64 iva_read(void)
{
__u64 v;
__asm__ volatile ("mov %0 = cr.iva\n" : "=r" (v));
return v;
}
/** Write IVA (Interruption Vector Address) register.
*
* @param New location of interruption vector table.
*/
static inline void iva_write(__u64 v)
{
__asm__ volatile ("mov cr.iva = %0\n" : : "r" (v));
}
/** Read IVR (External Interrupt Vector Register).
*
* @return Highest priority, pending, unmasked external interrupt vector.
218,13 → 241,6
return (ipl_t) v;
}
#define set_shadow_register(reg,val) {__u64 v = val; __asm__ volatile("mov r15 = %0;;\n""bsw.0;;\n""mov " #reg " = r15;;\n""bsw.1;;\n" : : "r" (v) : "r15" ); }
#define get_shadow_register(reg,val) {__u64 v ; __asm__ volatile("bsw.0;;\n" "mov r15 = r" #reg ";;\n" "bsw.1;;\n" "mov %0 = r15;;\n" : "=r" (v) : : "r15" ); val=v; }
#define get_control_register(reg,val) {__u64 v ; __asm__ volatile("mov r15 = cr" #reg ";;\n" "mov %0 = r15;;\n" : "=r" (v) : : "r15" ); val=v; }
#define get_aplication_register(reg,val) {__u64 v ; __asm__ volatile("mov r15 = ar" #reg ";;\n" "mov %0 = r15;;\n" : "=r" (v) : : "r15" ); val=v; }
#define get_psr(val) {__u64 v ; __asm__ volatile("mov r15 = psr;;\n" "mov %0 = r15;;\n" : "=r" (v) : : "r15" ); val=v; }
extern void cpu_halt(void);
extern void cpu_sleep(void);
extern void asm_delay_loop(__u32 t);

/SPARTAN/trunk/arch/ia64/include/register.h
34,6 → 34,80
#define CR_IVR_MASK 0xf
#define PSR_I_MASK 0x4000
/** Application registers. */
#define AR_KR0 0
#define AR_KR1 1
#define AR_KR2 2
#define AR_KR3 3
#define AR_KR4 4
#define AR_KR5 5
#define AR_KR6 6
#define AR_KR7 7
/* AR 8-15 reserved */
#define AR_RSC 16
#define AR_BSP 17
#define AR_BSPSTORE 18
#define AR_RNAT 19
/* AR 20 reserved */
#define AR_FCR 21
/* AR 22-23 reserved */
#define AR_EFLAG 24
#define AR_CSD 25
#define AR_SSD 26
#define AR_CFLG 27
#define AR_FSR 28
#define AR_FIR 29
#define AR_FDR 30
/* AR 31 reserved */
#define AR_CCV 32
/* AR 33-35 reserved */
#define AR_UNAT 36
/* AR 37-39 reserved */
#define AR_FPSR 40
/* AR 41-43 reserved */
#define AR_ITC 44
/* AR 45-47 reserved */
/* AR 48-63 ignored */
#define AR_PFS 64
#define AR_LC 65
#define AR_EC 66
/* AR 67-111 reserved */
/* AR 112-127 ignored */
/** Control registers. */
#define CR_DCR 0
#define CR_ITM 1
#define CR_IVA 2
/* CR3-CR7 reserved */
#define CR_PTA 8
/* CR9-CR15 reserved */
#define CR_IPSR 16
#define CR_ISR 17
/* CR18 reserved */
#define CR_IIP 19
#define CR_IFA 20
#define CR_ITIR 21
#define CR_IIPA 22
#define CR_IFS 23
#define CR_IIM 24
#define CR_IHA 25
/* CR26-CR63 reserved */
#define CR_LID 64
#define CR_IVR 65
#define CR_TPR 66
#define CR_EOI 67
#define CR_IRR0 68
#define CR_IRR1 69
#define CR_IRR2 70
#define CR_IRR3 71
#define CR_ITV 72
#define CR_PMV 73
#define CR_CMCV 74
/* CR75-CR79 reserved */
#define CR_LRR0 80
#define CR_LRR1 81
/* CR82-CR127 reserved */
/** External Interrupt Vector Register */
union cr_ivr {
__u8 vector;

/SPARTAN/trunk/arch/ia64/Makefile.inc
54,7 → 54,6
arch/$(ARCH)/src/cpu/cpu.c \
arch/$(ARCH)/src/ivt.S \
arch/$(ARCH)/src/interrupt.c \
arch/$(ARCH)/src/interrupt_handler.c \
arch/$(ARCH)/src/fmath.c \
arch/$(ARCH)/src/mm/frame.c \
arch/$(ARCH)/src/drivers/it.c

/SPARTAN/trunk/arch/ia64/src/interrupt_handler.c
File deleted

/SPARTAN/trunk/arch/ia64/src/ivt.S
50,9 → 50,17
* @param offs Offset from the beginning of IVT.
* @param handler Interrupt handler address.
*/
.macro HEAVYWEIGHT_HANDLER offs handler
.org IVT + \offs
.macro HEAVYWEIGHT_HANDLER offs, handler=universal_handler
.org ivt + \offs
mov r24 = \offs
movl r25 = \handler ;;
mov ar.k0 = r24
mov ar.k1 = r25
br heavyweight_handler
.endm
.global heavyweight_handler
heavyweight_handler:
/* 1. copy interrupt registers into bank 0 */
mov r24 = cr.iip
mov r25 = cr.ipsr
67,10 → 75,10
/* TODO: support interruptions from userspace */
/* assume kernel stack */
/* 4. save registers in bank 0 into memory stack */
add r31 = -8, r12 ;;
add r12 = -STACK_FRAME_SIZE, r12 ;;
add r12 = -STACK_FRAME_SIZE, r12
/* 4. save registers in bank 0 into memory stack */
st8 [r31] = r29, -8 ;; /* save predicate registers */
st8 [r31] = r24, -8 ;; /* save cr.iip */
77,47 → 85,94
st8 [r31] = r25, -8 ;; /* save cr.ipsr */
st8 [r31] = r26, -8 ;; /* save cr.iipa */
st8 [r31] = r27, -8 ;; /* save cr.isr */
st8 [r31] = r28, -8 ;; /* save cr.ifa */
st8 [r31] = r28, -8 /* save cr.ifa */
/* 5. RSE switch from interrupted context */
.auto
mov r24 = ar.rsc
mov r25 = ar.pfs
cover
mov r26 = cr.ifs
st8 [r31] = r24, -8 /* save ar.rsc */
st8 [r31] = r25, -8 /* save ar.pfs */
st8 [r31] = r24, -8;; /* save ar.rsc */
st8 [r31] = r25, -8;; /* save ar.pfs */
st8 [r31] = r26, -8 /* save ar.ifs */
and r30 = ~3, r24
mov ar.rsc = r30 /* place RSE in enforced lazy mode */
and r30 = ~3, r24 ;;
mov ar.rsc = r30 ;; /* place RSE in enforced lazy mode */
mov r27 = ar.rnat
mov r28 = ar.bspstore
mov r28 = ar.bspstore ;;
/* assume kernel backing store */
mov ar.bspstore = r28
mov ar.bspstore = r28 ;;
mov r29 = ar.bsp
st8 [r31] = r27, -8 /* save ar.rnat */
st8 [r31] = r28, -8 /* save ar.bspstore */
st8 [r31] = r27, -8 ;; /* save ar.rnat */
st8 [r31] = r28, -8 ;; /* save ar.bspstore */
st8 [r31] = r29, -8 /* save ar.bsp */
mov ar.rsc = r24 /* restore RSE's setting */
.explicit
/* the rest of the save-handler can be kept outside IVT */
movl r24 = \handler
mov r25 = b0
/* steps 6 - 15 are done by heavyweight_handler_inner() */
mov r24 = b0 /* save b0 belonging to interrupted context */
mov r26 = ar.k0
mov r25 = ar.k1
br.call.sptk.many rp = heavyweight_handler_inner
0: mov b0 = r25
0: mov b0 = r24 /* restore b0 belonging to the interrupted context */
br heavyweight_handler_finalize
.endm
/* 16. RSE switch to interrupted context */
cover /* allocate zerro size frame (step 1 (from Intel Docs)) */
add r31 = STACK_SCRATCH_AREA_SIZE, r12 ;;
mov r28 = ar.bspstore /* calculate loadrs (step 2) */
ld8 r29 = [r31], +8 ;; /* load ar.bsp */
sub r27 = r29 , r28 ;;
shl r27 = r27, 16
mov r24 = ar.rsc ;;
and r30 = ~3, r24 ;;
or r24 = r30 , r27 ;;
mov ar.rsc = r24 ;; /* place RSE in enforced lazy mode */
loadrs /* (step 3) */
ld8 r28 = [r31], +8 ;; /* load ar.bspstore */
ld8 r27 = [r31], +8 ;; /* load ar.rnat */
ld8 r26 = [r31], +8 ;; /* load cr.ifs */
ld8 r25 = [r31], +8 ;; /* load ar.pfs */
ld8 r24 = [r31], +8 ;; /* load ar.rsc */
mov ar.bspstore = r28 ;; /* (step 4) */
mov ar.rnat = r27 /* (step 5) */
mov ar.pfs = r25 /* (step 6) */
mov cr.ifs = r26
mov ar.rsc = r24 /* (step 7) */
/* 17. restore interruption state from memory stack */
ld8 r28 = [r31], +8 ;; /* load cr.ifa */
ld8 r27 = [r31], +8 ;; /* load cr.isr */
ld8 r26 = [r31], +8 ;; /* load cr.iipa */
ld8 r25 = [r31], +8 ;; /* load cr.ipsr */
ld8 r24 = [r31], +8 ;; /* load cr.iip */
mov cr.iip = r24
mov cr.ipsr = r25
mov cr.iipa = r26
mov cr.isr = r27
mov cr.ifa = r28
/* 18. restore predicate registers from memory stack */
ld8 r29 = [r31] , -8 ;; /* load predicate registers */
mov pr = r29
/* 19. return from interruption */
add r12 = STACK_FRAME_SIZE, r12
rfi ;;
.global heavyweight_handler_inner
heavyweight_handler_inner:
/*
124,10 → 179,14
* From this point, the rest of the interrupted context
* will be preserved in stacked registers and backing store.
*/
alloc loc0 = ar.pfs, 0, 46, 0, 0 ;;
alloc loc0 = ar.pfs, 0, 47, 2, 0 ;;
/* copy handler address (r24 from bank 0 will be invisible soon) */
mov loc1 = r24
/* bank 0 is going to be shadowed, copy essential data from there */
mov loc1 = r24 /* b0 belonging to interrupted context */
mov loc2 = r25
mov out0 = r26
add out1 = STACK_SCRATCH_AREA_SIZE, r12
/* 6. switch to bank 1 and reenable PSR.ic */
ssm 0x2000
135,60 → 194,60
srlz.d
/* 7. preserve branch and application registers */
mov loc2 = ar.unat
mov loc3 = ar.lc
mov loc4 = ar.ec
mov loc5 = ar.ccv
mov loc6 = ar.csd
mov loc7 = ar.ssd
mov loc3 = ar.unat
mov loc4 = ar.lc
mov loc5 = ar.ec
mov loc6 = ar.ccv
mov loc7 = ar.csd
mov loc8 = ar.ssd
mov loc8 = b0
mov loc9 = b1
mov loc10 = b2
mov loc11 = b3
mov loc12 = b4
mov loc13 = b5
mov loc14 = b6
mov loc15 = b7
mov loc9 = b0
mov loc10 = b1
mov loc11 = b2
mov loc12 = b3
mov loc13 = b4
mov loc14 = b5
mov loc15 = b6
mov loc16 = b7
/* 8. preserve general and floating-point registers */
/* TODO: save floating-point context */
mov loc16 = r1
mov loc17 = r2
mov loc18 = r3
mov loc19 = r4
mov loc20 = r5
mov loc21 = r6
mov loc22 = r7
mov loc23 = r8
mov loc24 = r9
mov loc25 = r10
mov loc26 = r11
mov loc17 = r1
mov loc18 = r2
mov loc19 = r3
mov loc20 = r4
mov loc21 = r5
mov loc22 = r6
mov loc23 = r7
mov loc24 = r8
mov loc25 = r9
mov loc26 = r10
mov loc27 = r11
/* skip r12 (stack pointer) */
mov loc27 = r13
mov loc28 = r14
mov loc29 = r15
mov loc30 = r16
mov loc31 = r17
mov loc32 = r18
mov loc33 = r19
mov loc34 = r20
mov loc35 = r21
mov loc36 = r22
mov loc37 = r23
mov loc38 = r24
mov loc39 = r25
mov loc40 = r26
mov loc41 = r27
mov loc42 = r28
mov loc43 = r29
mov loc44 = r30
mov loc45 = r31
mov loc28 = r13
mov loc29 = r14
mov loc30 = r15
mov loc31 = r16
mov loc32 = r17
mov loc33 = r18
mov loc34 = r19
mov loc35 = r20
mov loc36 = r21
mov loc37 = r22
mov loc38 = r23
mov loc39 = r24
mov loc40 = r25
mov loc41 = r26
mov loc42 = r27
mov loc43 = r28
mov loc44 = r29
mov loc45 = r30
mov loc46 = r31
/* 9. skipped (will not enable interrupts) */
/* 10. call handler */
mov b1 = loc1
mov b1 = loc2
br.call.sptk.many b0 = b1
/* 11. return from handler */
198,54 → 257,54
/* 13. restore general and floating-point registers */
/* TODO: restore floating-point context */
mov r1 = loc16
mov r2 = loc17
mov r3 = loc18
mov r4 = loc19
mov r5 = loc20
mov r6 = loc21
mov r7 = loc22
mov r8 = loc23
mov r9 = loc24
mov r10 = loc25
mov r11 = loc26
mov r1 = loc17
mov r2 = loc18
mov r3 = loc19
mov r4 = loc20
mov r5 = loc21
mov r6 = loc22
mov r7 = loc23
mov r8 = loc24
mov r9 = loc25
mov r10 = loc26
mov r11 = loc27
/* skip r12 (stack pointer) */
mov r13 = loc27
mov r14 = loc28
mov r15 = loc29
mov r16 = loc30
mov r17 = loc31
mov r18 = loc32
mov r19 = loc33
mov r20 = loc34
mov r21 = loc35
mov r22 = loc36
mov r23 = loc37
mov r24 = loc38
mov r25 = loc39
mov r26 = loc40
mov r27 = loc41
mov r28 = loc42
mov r29 = loc43
mov r30 = loc44
mov r31 = loc45
mov r13 = loc28
mov r14 = loc29
mov r15 = loc30
mov r16 = loc31
mov r17 = loc32
mov r18 = loc33
mov r19 = loc34
mov r20 = loc35
mov r21 = loc36
mov r22 = loc37
mov r23 = loc38
mov r24 = loc39
mov r25 = loc40
mov r26 = loc41
mov r27 = loc42
mov r28 = loc43
mov r29 = loc44
mov r30 = loc45
mov r31 = loc46
/* 14. restore branch and application registers */
mov ar.unat = loc2
mov ar.lc = loc3
mov ar.ec = loc4
mov ar.ccv = loc5
mov ar.csd = loc6
mov ar.ssd = loc7
mov ar.unat = loc3
mov ar.lc = loc4
mov ar.ec = loc5
mov ar.ccv = loc6
mov ar.csd = loc7
mov ar.ssd = loc8
mov b0 = loc8
mov b1 = loc9
mov b2 = loc10
mov b3 = loc11
mov b4 = loc12
mov b5 = loc13
mov b6 = loc14
mov b7 = loc15
mov b0 = loc9
mov b1 = loc10
mov b2 = loc11
mov b3 = loc12
mov b4 = loc13
mov b5 = loc14
mov b6 = loc15
mov b7 = loc16
/* 15. disable PSR.ic and switch to bank 0 */
rsm 0x2000
252,492 → 311,81
bsw.0 ;;
srlz.d
mov r24 = loc1
mov ar.pfs = loc0
br.ret.sptk.many rp
br.ret.sptk.many b0
.global heavyweight_handler_finalize
heavyweight_handler_finalize:
/* 16. RSE switch to interrupted context */
.auto
cover /* allocate zerro size frame (step 1 (from Intel Docs)) */
.global ivt
.align 32768
ivt:
HEAVYWEIGHT_HANDLER 0x0000
HEAVYWEIGHT_HANDLER 0x0400
HEAVYWEIGHT_HANDLER 0x0800
HEAVYWEIGHT_HANDLER 0x0c00
HEAVYWEIGHT_HANDLER 0x1000
HEAVYWEIGHT_HANDLER 0x1400
HEAVYWEIGHT_HANDLER 0x1800
HEAVYWEIGHT_HANDLER 0x1c00
HEAVYWEIGHT_HANDLER 0x2000
HEAVYWEIGHT_HANDLER 0x2400
HEAVYWEIGHT_HANDLER 0x2800
HEAVYWEIGHT_HANDLER 0x2c00 break_instruction
HEAVYWEIGHT_HANDLER 0x3000 external_interrupt /* For external interrupt, heavyweight handler is used. */
HEAVYWEIGHT_HANDLER 0x3400
HEAVYWEIGHT_HANDLER 0x3800
HEAVYWEIGHT_HANDLER 0x3c00
HEAVYWEIGHT_HANDLER 0x4000
HEAVYWEIGHT_HANDLER 0x4400
HEAVYWEIGHT_HANDLER 0x4800
HEAVYWEIGHT_HANDLER 0x4c00
add r31 = STACK_SCRATCH_AREA_SIZE, r12
mov r28 = ar.bspstore /* calculate loadrs (step 2) */
ld8 r29 = [r31], +8 /* load ar.bsp */
sub r27 = r29 , r28
shl r27 = r27, 16
mov r24 = ar.rsc
and r30 = ~3, r24
or r24 = r30 , r27
mov ar.rsc = r24 /* place RSE in enforced lazy mode */
loadrs /* (step 3) */
ld8 r28 = [r31], +8 /* load ar.bspstore */
ld8 r27 = [r31], +8 /* load ar.rnat */
ld8 r26 = [r31], +8 /* load cr.ifs */
ld8 r25 = [r31], +8 /* load ar.pfs */
ld8 r24 = [r31], +8 /* load ar.rsc */
mov ar.bspstore = r28 /* (step 4) */
mov ar.rnat = r27 /* (step 5) */
mov ar.pfs = r25 /* (step 6) */
mov cr.ifs = r26
mov ar.rsc = r24 /* (step 7) */
.explicit
/* 17. restore interruption state from memory stack */
ld8 r28 = [r31], +8 ;; /* load cr.ifa */
ld8 r27 = [r31], +8 ;; /* load cr.isr */
ld8 r26 = [r31], +8 ;; /* load cr.iipa */
ld8 r25 = [r31], +8 ;; /* load cr.ipsr */
ld8 r24 = [r31], +8 ;; /* load cr.iip */
mov cr.iip = r24
mov cr.ipsr = r25
mov cr.iipa = r26
mov cr.isr = r27
mov cr.ifa = r28
/* 18. restore predicate registers from memory stack */
ld8 r29 = [r31] , -8 ;; /* load predicate registers */
mov pr = r29
HEAVYWEIGHT_HANDLER 0x5000
HEAVYWEIGHT_HANDLER 0x5100
HEAVYWEIGHT_HANDLER 0x5200
HEAVYWEIGHT_HANDLER 0x5300
HEAVYWEIGHT_HANDLER 0x5400 general_exception
HEAVYWEIGHT_HANDLER 0x5500
HEAVYWEIGHT_HANDLER 0x5600
HEAVYWEIGHT_HANDLER 0x5700
HEAVYWEIGHT_HANDLER 0x5800
HEAVYWEIGHT_HANDLER 0x5900
HEAVYWEIGHT_HANDLER 0x5a00
HEAVYWEIGHT_HANDLER 0x5b00
HEAVYWEIGHT_HANDLER 0x5c00
HEAVYWEIGHT_HANDLER 0x5d00
HEAVYWEIGHT_HANDLER 0x5e00
HEAVYWEIGHT_HANDLER 0x5f00
/* 19. return from interruption */
add r12 = STACK_FRAME_SIZE, r12
rfi ;;
HEAVYWEIGHT_HANDLER 0x6000
HEAVYWEIGHT_HANDLER 0x6100
HEAVYWEIGHT_HANDLER 0x6200
HEAVYWEIGHT_HANDLER 0x6300
HEAVYWEIGHT_HANDLER 0x6400
HEAVYWEIGHT_HANDLER 0x6500
HEAVYWEIGHT_HANDLER 0x6600
HEAVYWEIGHT_HANDLER 0x6700
HEAVYWEIGHT_HANDLER 0x6800
HEAVYWEIGHT_HANDLER 0x6900
HEAVYWEIGHT_HANDLER 0x6a00
HEAVYWEIGHT_HANDLER 0x6b00
HEAVYWEIGHT_HANDLER 0x6c00
HEAVYWEIGHT_HANDLER 0x6d00
HEAVYWEIGHT_HANDLER 0x6e00
HEAVYWEIGHT_HANDLER 0x6f00
dump_gregs:
mov r16 = REG_DUMP;;
st8 [r16] = r0;;
add r16 = 8,r16 ;;
st8 [r16] = r1;;
add r16 = 8,r16 ;;
st8 [r16] = r2;;
add r16 = 8,r16 ;;
st8 [r16] = r3;;
add r16 = 8,r16 ;;
st8 [r16] = r4;;
add r16 = 8,r16 ;;
st8 [r16] = r5;;
add r16 = 8,r16 ;;
st8 [r16] = r6;;
add r16 = 8,r16 ;;
st8 [r16] = r7;;
add r16 = 8,r16 ;;
st8 [r16] = r8;;
add r16 = 8,r16 ;;
st8 [r16] = r9;;
add r16 = 8,r16 ;;
st8 [r16] = r10;;
add r16 = 8,r16 ;;
st8 [r16] = r11;;
add r16 = 8,r16 ;;
st8 [r16] = r12;;
add r16 = 8,r16 ;;
st8 [r16] = r13;;
add r16 = 8,r16 ;;
st8 [r16] = r14;;
add r16 = 8,r16 ;;
st8 [r16] = r15;;
add r16 = 8,r16 ;;
bsw.1;;
mov r15 = r16;;
bsw.0;;
st8 [r16] = r15;;
add r16 = 8,r16 ;;
bsw.1;;
mov r15 = r17;;
bsw.0;;
st8 [r16] = r15;;
add r16 = 8,r16 ;;
bsw.1;;
mov r15 = r18;;
bsw.0;;
st8 [r16] = r15;;
add r16 = 8,r16 ;;
bsw.1;;
mov r15 = r19;;
bsw.0;;
st8 [r16] = r15;;
add r16 = 8,r16 ;;
bsw.1;;
mov r15 = r20;;
bsw.0;;
st8 [r16] = r15;;
add r16 = 8,r16 ;;
bsw.1;;
mov r15 = r21;;
bsw.0;;
st8 [r16] = r15;;
add r16 = 8,r16 ;;
bsw.1;;
mov r15 = r22;;
bsw.0;;
st8 [r16] = r15;;
add r16 = 8,r16 ;;
bsw.1;;
mov r15 = r23;;
bsw.0;;
st8 [r16] = r15;;
add r16 = 8,r16 ;;
bsw.1;;
mov r15 = r24;;
bsw.0;;
st8 [r16] = r15;;
add r16 = 8,r16 ;;
bsw.1;;
mov r15 = r25;;
bsw.0;;
st8 [r16] = r15;;
add r16 = 8,r16 ;;
bsw.1;;
mov r15 = r26;;
bsw.0;;
st8 [r16] = r15;;
add r16 = 8,r16 ;;
bsw.1;;
mov r15 = r27;;
bsw.0;;
st8 [r16] = r15;;
add r16 = 8,r16 ;;
bsw.1;;
mov r15 = r28;;
bsw.0;;
st8 [r16] = r15;;
add r16 = 8,r16 ;;
bsw.1;;
mov r15 = r29;;
bsw.0;;
st8 [r16] = r15;;
add r16 = 8,r16 ;;
bsw.1;;
mov r15 = r30;;
bsw.0;;
st8 [r16] = r15;;
add r16 = 8,r16 ;;
bsw.1;;
mov r15 = r31;;
bsw.0;;
st8 [r16] = r15;;
add r16 = 8,r16 ;;
st8 [r16] = r32;;
add r16 = 8,r16 ;;
st8 [r16] = r33;;
add r16 = 8,r16 ;;
st8 [r16] = r34;;
add r16 = 8,r16 ;;
st8 [r16] = r35;;
add r16 = 8,r16 ;;
st8 [r16] = r36;;
add r16 = 8,r16 ;;
st8 [r16] = r37;;
add r16 = 8,r16 ;;
st8 [r16] = r38;;
add r16 = 8,r16 ;;
st8 [r16] = r39;;
add r16 = 8,r16 ;;
st8 [r16] = r40;;
add r16 = 8,r16 ;;
st8 [r16] = r41;;
add r16 = 8,r16 ;;
st8 [r16] = r42;;
add r16 = 8,r16 ;;
st8 [r16] = r43;;
add r16 = 8,r16 ;;
st8 [r16] = r44;;
add r16 = 8,r16 ;;
st8 [r16] = r45;;
add r16 = 8,r16 ;;
st8 [r16] = r46;;
add r16 = 8,r16 ;;
st8 [r16] = r47;;
add r16 = 8,r16 ;;
st8 [r16] = r48;;
add r16 = 8,r16 ;;
st8 [r16] = r49;;
add r16 = 8,r16 ;;
st8 [r16] = r50;;
add r16 = 8,r16 ;;
st8 [r16] = r51;;
add r16 = 8,r16 ;;
st8 [r16] = r52;;
add r16 = 8,r16 ;;
st8 [r16] = r53;;
add r16 = 8,r16 ;;
st8 [r16] = r54;;
add r16 = 8,r16 ;;
st8 [r16] = r55;;
add r16 = 8,r16 ;;
st8 [r16] = r56;;
add r16 = 8,r16 ;;
st8 [r16] = r57;;
add r16 = 8,r16 ;;
st8 [r16] = r58;;
add r16 = 8,r16 ;;
st8 [r16] = r59;;
add r16 = 8,r16 ;;
st8 [r16] = r60;;
add r16 = 8,r16 ;;
st8 [r16] = r61;;
add r16 = 8,r16 ;;
st8 [r16] = r62;;
add r16 = 8,r16 ;;
st8 [r16] = r63;;
add r16 = 8,r16 ;;
st8 [r16] = r64;;
add r16 = 8,r16 ;;
st8 [r16] = r65;;
add r16 = 8,r16 ;;
st8 [r16] = r66;;
add r16 = 8,r16 ;;
st8 [r16] = r67;;
add r16 = 8,r16 ;;
st8 [r16] = r68;;
add r16 = 8,r16 ;;
st8 [r16] = r69;;
add r16 = 8,r16 ;;
st8 [r16] = r70;;
add r16 = 8,r16 ;;
st8 [r16] = r71;;
add r16 = 8,r16 ;;
st8 [r16] = r72;;
add r16 = 8,r16 ;;
st8 [r16] = r73;;
add r16 = 8,r16 ;;
st8 [r16] = r74;;
add r16 = 8,r16 ;;
st8 [r16] = r75;;
add r16 = 8,r16 ;;
st8 [r16] = r76;;
add r16 = 8,r16 ;;
st8 [r16] = r77;;
add r16 = 8,r16 ;;
st8 [r16] = r78;;
add r16 = 8,r16 ;;
st8 [r16] = r79;;
add r16 = 8,r16 ;;
st8 [r16] = r80;;
add r16 = 8,r16 ;;
st8 [r16] = r81;;
add r16 = 8,r16 ;;
st8 [r16] = r82;;
add r16 = 8,r16 ;;
st8 [r16] = r83;;
add r16 = 8,r16 ;;
st8 [r16] = r84;;
add r16 = 8,r16 ;;
st8 [r16] = r85;;
add r16 = 8,r16 ;;
st8 [r16] = r86;;
add r16 = 8,r16 ;;
st8 [r16] = r87;;
add r16 = 8,r16 ;;
st8 [r16] = r88;;
add r16 = 8,r16 ;;
st8 [r16] = r89;;
add r16 = 8,r16 ;;
st8 [r16] = r90;;
add r16 = 8,r16 ;;
st8 [r16] = r91;;
add r16 = 8,r16 ;;
st8 [r16] = r92;;
add r16 = 8,r16 ;;
st8 [r16] = r93;;
add r16 = 8,r16 ;;
st8 [r16] = r94;;
add r16 = 8,r16 ;;
st8 [r16] = r95;;
add r16 = 8,r16 ;;
st8 [r16] = r96;;
add r16 = 8,r16 ;;
st8 [r16] = r97;;
add r16 = 8,r16 ;;
st8 [r16] = r98;;
add r16 = 8,r16 ;;
st8 [r16] = r99;;
add r16 = 8,r16 ;;
st8 [r16] = r100;;
add r16 = 8,r16 ;;
st8 [r16] = r101;;
add r16 = 8,r16 ;;
st8 [r16] = r102;;
add r16 = 8,r16 ;;
st8 [r16] = r103;;
add r16 = 8,r16 ;;
st8 [r16] = r104;;
add r16 = 8,r16 ;;
st8 [r16] = r105;;
add r16 = 8,r16 ;;
st8 [r16] = r106;;
add r16 = 8,r16 ;;
st8 [r16] = r107;;
add r16 = 8,r16 ;;
st8 [r16] = r108;;
add r16 = 8,r16 ;;
st8 [r16] = r109;;
add r16 = 8,r16 ;;
st8 [r16] = r110;;
add r16 = 8,r16 ;;
st8 [r16] = r111;;
add r16 = 8,r16 ;;
st8 [r16] = r112;;
add r16 = 8,r16 ;;
st8 [r16] = r113;;
add r16 = 8,r16 ;;
st8 [r16] = r114;;
add r16 = 8,r16 ;;
st8 [r16] = r115;;
add r16 = 8,r16 ;;
st8 [r16] = r116;;
add r16 = 8,r16 ;;
st8 [r16] = r117;;
add r16 = 8,r16 ;;
st8 [r16] = r118;;
add r16 = 8,r16 ;;
st8 [r16] = r119;;
add r16 = 8,r16 ;;
st8 [r16] = r120;;
add r16 = 8,r16 ;;
st8 [r16] = r121;;
add r16 = 8,r16 ;;
st8 [r16] = r122;;
add r16 = 8,r16 ;;
st8 [r16] = r123;;
add r16 = 8,r16 ;;
st8 [r16] = r124;;
add r16 = 8,r16 ;;
st8 [r16] = r125;;
add r16 = 8,r16 ;;
st8 [r16] = r126;;
add r16 = 8,r16 ;;
st8 [r16] = r127;;
add r16 = 8,r16 ;;
br.ret.sptk.many b0;;
.macro Handler o h
.org IVT + \o
br \h;;
.endm
.macro Handler2 o
.org IVT + \o
br.call.sptk.many b0 = dump_gregs;;
mov r16 = \o ;;
bsw.1;;
br universal_handler;;
.endm
.global IVT
.align 32768
IVT:
Handler2 0x0000
Handler2 0x0400
Handler2 0x0800
Handler2 0x0c00
Handler2 0x1000
Handler2 0x1400
Handler2 0x1800
Handler2 0x1c00
Handler2 0x2000
Handler2 0x2400
Handler2 0x2800
Handler 0x2c00 break_instruction
HEAVYWEIGHT_HANDLER 0x3000 external_interrupt /* For external interrupt, heavyweight handler is used. */
Handler2 0x3400
Handler2 0x3800
Handler2 0x3c00
Handler2 0x4000
Handler2 0x4400
Handler2 0x4800
Handler2 0x4c00
Handler2 0x5000
Handler2 0x5100
Handler2 0x5200
Handler2 0x5300
#Handler 0x5400 general_exception
Handler2 0x5400
Handler2 0x5500
Handler2 0x5600
Handler2 0x5700
Handler2 0x5800
Handler2 0x5900
Handler2 0x5a00
Handler2 0x5b00
Handler2 0x5c00
Handler2 0x5d00
Handler2 0x5e00
Handler2 0x5f00
Handler2 0x6000
Handler2 0x6100
Handler2 0x6200
Handler2 0x6300
Handler2 0x6400
Handler2 0x6500
Handler2 0x6600
Handler2 0x6700
Handler2 0x6800
Handler2 0x6900
Handler2 0x6a00
Handler2 0x6b00
Handler2 0x6c00
Handler2 0x6d00
Handler2 0x6e00
Handler2 0x6f00
Handler2 0x7000
Handler2 0x7100
Handler2 0x7200
Handler2 0x7300
Handler2 0x7400
Handler2 0x7500
Handler2 0x7600
Handler2 0x7700
Handler2 0x7800
Handler2 0x7900
Handler2 0x7a00
Handler2 0x7b00
Handler2 0x7c00
Handler2 0x7d00
Handler2 0x7e00
Handler2 0x7f00
.align 32768
.global REG_DUMP
REG_DUMP:
.space 128*8
HEAVYWEIGHT_HANDLER 0x7000
HEAVYWEIGHT_HANDLER 0x7100
HEAVYWEIGHT_HANDLER 0x7200
HEAVYWEIGHT_HANDLER 0x7300
HEAVYWEIGHT_HANDLER 0x7400
HEAVYWEIGHT_HANDLER 0x7500
HEAVYWEIGHT_HANDLER 0x7600
HEAVYWEIGHT_HANDLER 0x7700
HEAVYWEIGHT_HANDLER 0x7800
HEAVYWEIGHT_HANDLER 0x7900
HEAVYWEIGHT_HANDLER 0x7a00
HEAVYWEIGHT_HANDLER 0x7b00
HEAVYWEIGHT_HANDLER 0x7c00
HEAVYWEIGHT_HANDLER 0x7d00
HEAVYWEIGHT_HANDLER 0x7e00
HEAVYWEIGHT_HANDLER 0x7f00

/SPARTAN/trunk/arch/ia64/src/ia64.c
29,9 → 29,16
#include <arch.h>
#include <arch/ski/ski.h>
#include <arch/drivers/it.h>
#include <arch/interrupt.h>
#include <arch/barrier.h>
#include <arch/types.h>
void arch_pre_mm_init(void)
{
/* Set Interruption Vector Address (i.e. location of interruption vector table). */
iva_write((__address) &ivt);
srlz_d();
ski_init_console();
it_init();
}

/SPARTAN/trunk/arch/ia64/src/cpu/cpu.c
3,41 → 3,24
#include <panic.h>
#include <arch/types.h>
extern int IVT;
void cpu_arch_init(void)
{
int *p=&IVT;
volatile __u64 hlp,hlp2;
int psr = 0x2000;
int psr = 0x2000;
__asm__ volatile (
"mov cr2 = %0;;\n"
"{mov psr.l = %1;;}\n"
"{mov psr.l = %0 ;;}\n"
"{srlz.i;"
"srlz.d;;}"
"srlz.d ;;}"
:
: "r" (p), "r" (psr)
: "r" (psr)
);
/*Switch register bank of regs r16 .. r31 to 1 It is automaticly cleared on exception*/
/* Switch to register bank 1. */
__asm__ volatile
(
"bsw.1;;\n"
);
}

/SPARTAN/trunk/arch/ia64/src/interrupt.c
1,5 → 1,6
/*
* Copyright (C) 2005 Jakub Jermar
* Copyright (C) 2005 Jakub Vana
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
36,9 → 37,125
#include <arch/register.h>
#include <arch/drivers/it.h>
#include <arch.h>
#include <symtab.h>
#include <debug.h>
void external_interrupt(void)
#define VECTORS_64_BUNDLE 20
#define VECTORS_16_BUNDLE 48
#define VECTORS_16_BUNDLE_START 0x5000
#define VECTOR_MAX 0x7f00
#define BUNDLE_SIZE 16
char *vector_names_64_bundle[VECTORS_64_BUNDLE] = {
"VHPT Translation vector",
"Instruction TLB vector",
"Data TLB vector",
"Alternate Instruction TLB vector",
"Alternate Data TLB vector",
"Data Nested TLB vector",
"Instruction Key Miss vector",
"Data Key Miss vector",
"Dirty-Bit vector",
"Instruction Access-Bit vector",
"Data Access-Bit vector"
"Break Instruction vector",
"External Interrupt vector"
"Reserved",
"Reserved",
"Reserved",
"Reserved",
"Reserved",
"Reserved",
"Reserved"
};
char *vector_names_16_bundle[VECTORS_16_BUNDLE] = {
"Page Not Present vector",
"Key Permission vector",
"Instruction Access rights vector",
"Data Access Rights vector",
"General Exception vector",
"Disabled FP-Register vector",
"NaT Consumption vector",
"Speculation vector",
"Reserved",
"Debug vector",
"Unaligned Reference vector",
"Unsupported Data Reference vector",
"Floating-point Fault vector",
"Floating-point Trap vector",
"Lower-Privilege Transfer Trap vector",
"Taken Branch Trap vector",
"Single STep Trap vector",
"Reserved",
"Reserved",
"Reserved",
"Reserved",
"Reserved",
"Reserved",
"Reserved",
"Reserved",
"IA-32 Exception vector",
"IA-32 Intercept vector",
"IA-32 Interrupt vector",
"Reserved",
"Reserved",
"Reserved"
};
static char *vector_to_string(__u16 vector);
static void dump_stack(struct exception_regdump *pstate);
char *vector_to_string(__u16 vector)
{
ASSERT(vector <= VECTOR_MAX);
if (vector >= VECTORS_16_BUNDLE_START)
return vector_names_16_bundle[(vector-VECTORS_16_BUNDLE_START)/(16*BUNDLE_SIZE)];
else
return vector_names_64_bundle[vector/(64*BUNDLE_SIZE)];
}
void dump_stack(struct exception_regdump *pstate)
{
char *ifa, *iipa, *iip;
ifa = get_symtab_entry(pstate->cr_ifa);
iipa = get_symtab_entry(pstate->cr_iipa);
iip = get_symtab_entry(pstate->cr_iip);
putchar('\n');
printf("ar.bsp=%P\tar.bspstore=%P\n", pstate->ar_bsp, pstate->ar_bspstore);
printf("ar.rnat=%Q\tar.rsc=%Q\n", pstate->ar_rnat, pstate->ar_rsc);
printf("ar.ifs=%Q\tar.pfs=%Q\n", pstate->ar_ifs, pstate->ar_pfs);
printf("cr.isr=%Q\tcr.ips=%Q\t\n", pstate->cr_isr, pstate->cr_ips);
printf("cr.iip=%Q (%s)\n", pstate->cr_iip, iip ? iip : "?");
printf("cr.iipa=%Q (%s)\n", pstate->cr_iipa, iipa ? iipa : "?");
printf("cr.ifa=%Q (%s)\n", pstate->cr_ifa, ifa ? ifa : "?");
}
void general_exception(__u64 vector, struct exception_regdump *pstate)
{
dump_stack(pstate);
panic("General Exception\n");
}
void break_instruction(__u64 vector, struct exception_regdump *pstate)
{
dump_stack(pstate);
panic("Break Instruction\n");
}
void universal_handler(__u64 vector, struct exception_regdump *pstate)
{
dump_stack(pstate);
panic("Interruption: %W (%s)\n", (__u16) vector, vector_to_string(vector));
}
void external_interrupt(__u64 vector, struct exception_regdump *pstate)
{
cr_ivr_t ivr;
ivr.value = ivr_read();