31,6 → 31,7 |
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#include <arch/types.h> |
#include <config.h> |
#include <arch/register.h> |
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/** Return base address of current stack |
* |
47,25 → 48,163 |
return v; |
} |
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/** Read IVR (External Interrupt Vector Register) |
/** Read IVR (External Interrupt Vector Register). |
* |
* @return Highest priority, pending, unmasked external interrupt vector. |
*/ |
static inline __u8 read_ivr(void) |
static inline __u64 ivr_read(void) |
{ |
__u64 v; |
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__asm__ volatile ("mov %0 = cr65\n" : "=r" (v)); |
__asm__ volatile ("mov %0 = cr.ivr\n" : "=r" (v)); |
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return (__u8) (v & 0xf); |
return v; |
} |
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/** Write ITC (Interval Timer Counter) register. |
* |
* @param New counter value. |
*/ |
static inline void itc_write(__u64 v) |
{ |
__asm__ volatile ("mov ar.itc = %0\n" : : "r" (v)); |
} |
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void cpu_sleep(void); |
/** Read ITC (Interval Timer Counter) register. |
* |
* @return Current counter value. |
*/ |
static inline __u64 itc_read(void) |
{ |
__u64 v; |
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__asm__ volatile ("mov %0 = ar.itc\n" : "=r" (v)); |
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return v; |
} |
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void asm_delay_loop(__u32 t); |
/** Write ITM (Interval Timer Match) register. |
* |
* @param New match value. |
*/ |
static inline void itm_write(__u64 v) |
{ |
__asm__ volatile ("mov cr.itm = %0\n" : : "r" (v)); |
} |
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/** Write ITV (Interval Timer Vector) register. |
* |
* @param New vector and masked bit. |
*/ |
static inline void itv_write(__u64 v) |
{ |
__asm__ volatile ("mov cr.itv = %0\n" : : "r" (v)); |
} |
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/** Write EOI (End Of Interrupt) register. |
* |
* @param This value is ignored. |
*/ |
static inline void eoi_write(__u64 v) |
{ |
__asm__ volatile ("mov cr.eoi = %0\n" : : "r" (v)); |
} |
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/** Read TPR (Task Priority Register). |
* |
* @return Current value of TPR. |
*/ |
static inline __u64 tpr_read(void) |
{ |
__u64 v; |
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__asm__ volatile ("mov %0 = cr.tpr\n" : "=r" (v)); |
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return v; |
} |
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/** Write TPR (Task Priority Register). |
* |
* @param New value of TPR. |
*/ |
static inline void tpr_write(__u64 v) |
{ |
__asm__ volatile ("mov cr.tpr = %0\n" : : "r" (v)); |
} |
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/** Disable interrupts. |
* |
* Disable interrupts and return previous |
* value of PSR. |
* |
* @return Old interrupt priority level. |
*/ |
static ipl_t interrupts_disable(void) |
{ |
__u64 v; |
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__asm__ volatile ( |
"mov %0 = psr\n" |
"rsm %1\n" |
: "=r" (v) |
: "i" (PSR_I_MASK) |
); |
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return (ipl_t) v; |
} |
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/** Enable interrupts. |
* |
* Enable interrupts and return previous |
* value of PSR. |
* |
* @return Old interrupt priority level. |
*/ |
static ipl_t interrupts_enable(void) |
{ |
__u64 v; |
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__asm__ volatile ( |
"mov %0 = psr\n" |
"ssm %1\n" |
";;\n" |
"srlz.d\n" |
: "=r" (v) |
: "i" (PSR_I_MASK) |
); |
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return (ipl_t) v; |
} |
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/** Restore interrupt priority level. |
* |
* Restore PSR. |
* |
* @param ipl Saved interrupt priority level. |
*/ |
static inline void interrupts_restore(ipl_t ipl) |
{ |
__asm__ volatile ( |
"mov psr.l = %0\n" |
";;\n" |
"srlz.d\n" |
: : "r" ((__u64) ipl) |
); |
} |
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/** Return interrupt priority level. |
* |
* @return PSR. |
*/ |
static inline ipl_t interrupts_read(void) |
{ |
__u64 v; |
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__asm__ volatile ("mov %0 = psr\n" : "=r" (v)); |
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return (ipl_t) v; |
} |
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#define set_shadow_register(reg,val) {__u64 v = val; __asm__ volatile("mov r15 = %0;;\n""bsw.0;;\n""mov " #reg " = r15;;\n""bsw.1;;\n" : : "r" (v) : "r15" ); } |
#define get_shadow_register(reg,val) {__u64 v ; __asm__ volatile("bsw.0;;\n" "mov r15 = r" #reg ";;\n" "bsw.1;;\n" "mov %0 = r15;;\n" : "=r" (v) : : "r15" ); val=v; } |
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73,10 → 212,8 |
#define get_aplication_register(reg,val) {__u64 v ; __asm__ volatile("mov r15 = ar" #reg ";;\n" "mov %0 = r15;;\n" : "=r" (v) : : "r15" ); val=v; } |
#define get_psr(val) {__u64 v ; __asm__ volatile("mov r15 = psr;;\n" "mov %0 = r15;;\n" : "=r" (v) : : "r15" ); val=v; } |
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extern void cpu_halt(void); |
extern void cpu_sleep(void); |
extern void asm_delay_loop(__u32 t); |
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void cpu_halt(void); |
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#endif |