| /SPARTAN/trunk/arch/ia32/src/cpu/cpu.c |
|---|
| 108,10 → 108,7 |
| /* |
| * Check for AMD processor. |
| */ |
| if (info.cpuid_ebx==AMD_CPUID_EBX && |
| info.cpuid_ecx==AMD_CPUID_ECX && |
| info.cpuid_edx==AMD_CPUID_EDX) { |
| if (info.cpuid_ebx==AMD_CPUID_EBX && info.cpuid_ecx==AMD_CPUID_ECX && info.cpuid_edx==AMD_CPUID_EDX) { |
| CPU->arch.vendor = VendorAMD; |
| } |
| 118,12 → 115,8 |
| /* |
| * Check for Intel processor. |
| */ |
| if (info.cpuid_ebx==INTEL_CPUID_EBX && |
| info.cpuid_ecx==INTEL_CPUID_ECX && |
| info.cpuid_edx==INTEL_CPUID_EDX) { |
| if (info.cpuid_ebx==INTEL_CPUID_EBX && info.cpuid_ecx==INTEL_CPUID_ECX && info.cpuid_edx==INTEL_CPUID_EDX) { |
| CPU->arch.vendor = VendorIntel; |
| } |
| cpuid(1, &info); |
| /SPARTAN/trunk/arch/ia32/src/pm.c |
|---|
| 74,7 → 74,6 |
| d->base_0_15 = base & 0xffff; |
| d->base_16_23 = ((base) >> 16) & 0xff; |
| d->base_24_31 = ((base) >> 24) & 0xff; |
| } |
| void gdt_setlimit(struct descriptor *d, __u32 limit) |
| /SPARTAN/trunk/arch/ia32/src/interrupt.c |
|---|
| 97,8 → 97,7 |
| void nm_fault(__u8 n, __u32 stack[]) |
| { |
| reset_TS_flag(); |
| if ((CPU->fpu_owner)!=NULL) |
| { |
| if ((CPU->fpu_owner)!=NULL) { |
| fpu_lazy_context_save(&((CPU->fpu_owner)->saved_fpu_context)); |
| (CPU->fpu_owner)->fpu_context_engaged=0; /* don't prevent migration */ |
| } |
| /SPARTAN/trunk/arch/ia32/src/drivers/i8254.c |
|---|
| 109,11 → 109,8 |
| o2 = inb(CLK_PORT1); |
| o2 |= inb(CLK_PORT1) << 8; |
| CPU->delay_loop_const = ((MAGIC_NUMBER*LOOPS)/1000) / ((t1-t2)-(o1-o2)) + (((MAGIC_NUMBER*LOOPS)/1000) % ((t1-t2)-(o1-o2)) ? 1 : 0); |
| CPU->delay_loop_const = ((MAGIC_NUMBER*LOOPS)/1000) / ((t1-t2)-(o1-o2)) + |
| (((MAGIC_NUMBER*LOOPS)/1000) % ((t1-t2)-(o1-o2)) ? 1 : 0); |
| clk1 = rdtsc(); |
| delay(1<<SHIFT); |
| clk2 = rdtsc(); |