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Compare Revisions

• This comparison shows the changes necessary to convert path

  → /SPARTAN/trunk/arch/ia32/ @ 232

  → /SPARTAN/trunk/arch/ia32 @ 230

  ↔ Reverse comparison

• Compare Path:	Rev

  With Path:	Rev

Ignore whitespace Rev 232 → Rev 230

/SPARTAN/trunk/arch/ia32/src/boot/boot.S
50,6 → 50,7
call memmap_arch_init
lgdt gdtr # initialize Global Descriptor Table register
lidt idtr # initialize Interrupt Descriptor Table register
movl %cr0,%eax
orl $0x1,%eax
72,6 → 73,7
movl $0x7c00, %esp # initialize stack pointer
lgdt gdtr
lidt idtr
meeting_point:
movw $16,%ax

/SPARTAN/trunk/arch/ia32/src/smp/ap.S
51,6 → 51,7
movw %ax,%ds
lgdt gdtr # initialize Global Descriptor Table register
lidt idtr # initialize Interrupt Descriptor Table register
movl %cr0,%eax
orl $1,%eax

/SPARTAN/trunk/arch/ia32/src/pm.c
165,16 → 165,7
{
struct descriptor *gdt_p = (struct descriptor *) PA2KA(gdtr.base);
/*
* Update addresses in GDT and IDT to their virtual counterparts.
*/
gdtr.base = KA2PA(gdtr.base);
idtr.base = (__address) idt;
__asm__ volatile ("lgdt %0\n" : : "m" (gdtr));
__asm__ volatile ("lidt %0\n" : : "m" (idtr));
/*
* Each CPU has its private GDT and TSS.
* All CPUs share one IDT.
*/
206,7 → 197,7
* As of this moment, the current CPU has its own GDT pointing
* to its own TSS. We just need to load the TR register.
*/
__asm__ volatile ("ltr %0" : : "r" ((__u16) selector(TSS_DES)));
__asm__("ltr %0" : : "r" ((__u16) selector(TSS_DES)));
clean_IOPL_NT_flags(); /* Disable I/O on nonprivileged levels */
clean_AM_flag(); /* Disable alignment check */