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Ignore whitespace Rev 205 → Rev 206

/SPARTAN/trunk/arch/amd64/src/delay.S
0,0 → 1,48
#
# Copyright (C) 2001-2004 Jakub Jermar
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
 
#
# Micro second delay loop functions.
#
 
.text
 
.global asm_delay_loop
.global asm_fake_loop
 
asm_delay_loop:
0: lahf
dec %edi
jnz 0b
ret
 
asm_fake_loop:
0: lahf
dec %edi
jz 0b
ret
/SPARTAN/trunk/arch/amd64/src/boot/boot.S
66,6 → 66,8
 
# Load gdtr, idtr
lgdt gdtr_inst
# Load idtr, but it contains mess - we should not get interrupt
# anyway
lidt idtr_inst
movl %cr0,%eax
72,7 → 74,7
orl $0x1,%eax
movl %eax,%cr0 # switch to protected mode
 
jmpl $selector(KTEXT32_DES), $now_in_prot
jmpl $gdtselector(KTEXT32_DES), $now_in_prot
 
no_long_mode:
1:
82,7 → 84,7
# the Default operand size must not be 1 when entering long mode
now_in_prot:
# Set up stack & data descriptors
movw $selector(KDATA_DES), %ax
movw $gdtselector(KDATA_DES), %ax
movw %ax, %ds
movw %ax, %fs
movw %ax, %gs
110,21 → 112,20
movl %eax, %cr0
# At this point we are in compatibility mode
jmpl $selector(KTEXT_DES), $start64
jmpl $gdtselector(KTEXT_DES), $start64
 
.code64
start64:
movq START_STACK_64, %rsp
lidt idtr_inst
call main_bsp # never returns
1:
jmp 1b
 
.section K_DATA_START
.align 4096
 
# Identical mapping of first 16MB and the same of -2GB -> 0
.global ptl_2
ptl_2:
.quad 0x0 | (PTL_WRITABLE | PTL_PRESENT | PTL_2MB_PAGE)
153,10 → 154,10
 
.global gdtr_inst
gdtr_inst:
.word selector(GDT_ITEMS)
.word gdtselector(GDT_ITEMS)
.long KA2PA(gdt)
 
.global idtr_inst
idtr_inst:
.word 0
.word idtselector(IDT_ITEMS)
.long KA2PA(idt)
/SPARTAN/trunk/arch/amd64/src/dummy.s
28,10 → 28,6
 
.text
 
.global cpu_priority_high
.global cpu_priority_low
.global cpu_priority_read
.global cpu_priority_restore
.global userspace
.global before_thread_runs_arch
.global panic_printf
40,27 → 36,51
.global cpu_sleep
.global cpu_print_report
.global get_memory_size
.global arch_pre_mm_init
.global arch_post_mm_init
.global arch_late_init
.global calibrate_delay_loop
.global asm_delay_loop
.global cpu_halt
.global page_arch_init
.global frame_arch_init
.global dummy
.global asm_delay_loop
.global trap_register
.global trap_virtual_eoi
.global trap_virtual_enable_irqs
.global rdtsc
.global trap_virtual_disable_irqs
.global enable_irqs_function
.global disable_irqs_function
.global eoi_function
.global syscall
.global null_interrupt
.global interrupt_handler_size
.global gp_fault
.global nm_fault
.global ss_fault
.global tss_p
.global interrupt_handlers
.global memcpy
 
cpu_priority_high:
cpu_priority_low:
cpu_priority_restore:
cpu_priority_read:
asm_delay_loop:
null_interrupt:
interrupt_handler_size:
interrupt_handlers:
gp_fault:
nm_fault:
ss_fault:
tss_p:
eoi_function:
syscall:
enable_irqs_function:
disable_irqs_function:
rdtsc:
trap_virtual_eoi:
trap_virtual_enable_irqs:
trap_virtual_disable_irqs:
trap_register:
before_thread_runs_arch:
userspace:
calibrate_delay_loop:
asm_delay_loop:
panic_printf:
cpu_identify:
cpu_arch_init:
67,8 → 87,6
cpu_sleep:
cpu_print_report:
get_memory_size:
arch_pre_mm_init:
arch_post_mm_init:
arch_late_init:
calibrate_delay_loop:
cpu_halt:
/SPARTAN/trunk/arch/amd64/src/amd64.c
0,0 → 1,66
/*
* Copyright (C) 2005 Ondrej Palkovsky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
 
#include <arch.h>
 
#include <arch/types.h>
 
#include <config.h>
 
#include <arch/ega.h>
#include <arch/i8042.h>
#include <arch/i8254.h>
#include <arch/i8259.h>
 
#include <arch/bios/bios.h>
 
void arch_pre_mm_init(void)
{
pm_init();
 
if (config.cpu_active == 1) {
bios_init();
i8042_init(); /* a20 bit */
i8259_init(); /* PIC */
i8254_init(); /* hard clock */
 
trap_register(VECTOR_SYSCALL, syscall);
#ifdef __SMP__
trap_register(VECTOR_TLB_SHOOTDOWN_IPI, tlb_shootdown_ipi);
trap_register(VECTOR_WAKEUP_IPI, wakeup_ipi);
#endif /* __SMP__ */
}
}
 
void arch_post_mm_init(void)
{
if (config.cpu_active == 1) {
ega_init(); /* video */
}
}
/SPARTAN/trunk/arch/amd64/src/pm.c
29,8 → 29,15
#include <arch/pm.h>
#include <arch/mm/page.h>
#include <arch/types.h>
#include <arch/interrupt.h>
#include <arch/asm.h>
 
#include <config.h>
 
#include <memstr.h>
#include <mm/heap.h>
#include <debug.h>
 
/*
* There is no segmentation in long mode so we set up flat mode. In this
* mode, we use, for each privilege level, two segments spanning the
71,7 → 78,7
.available = 0,
.longmode = 1,
.special = 0,
.granularity = 0,
.granularity = 1,
.base_24_31 = 0 },
/* UDATA descriptor */
{ .limit_0_15 = 0xffff,
95,13 → 102,157
.special = 0,
.granularity = 1,
.base_24_31 = 0 },
/* TSS descriptor - set up will be completed later */
/* TSS descriptor - set up will be completed later,
* on AMD64 it is 64-bit - 2 items in table */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
};
 
struct ptr_16_64 gdtr = {.limit = sizeof(gdtr), .base= (__u64) &gdtr };
 
struct idescriptor idt[IDT_ITEMS];
 
static struct tss tss;
 
/* Does not compile correctly if it does not exist */
/* TODO: Does not compile correctly if it does not exist ???? */
int __attribute__ ((section ("K_DATA_START"))) __fake;
 
void gdt_tss_setbase(struct descriptor *d, __address base)
{
struct tss_descriptor *td = (struct tss_descriptor *) d;
 
td->base_0_15 = base & 0xffff;
td->base_16_23 = ((base) >> 16) & 0xff;
td->base_24_31 = ((base) >> 24) & 0xff;
td->base_32_63 = ((base) >> 32);
}
 
void gdt_tss_setlimit(struct descriptor *d, __u32 limit)
{
struct tss_descriptor *td = (struct tss_descriptor *) d;
 
td->limit_0_15 = limit & 0xffff;
td->limit_16_19 = (limit >> 16) & 0xf;
}
 
void idt_setoffset(struct idescriptor *d, __address offset)
{
/*
* Offset is a linear address.
*/
d->offset_0_15 = offset & 0xffff;
d->offset_16_31 = offset >> 16 & 0xffff;
d->offset_32_63 = offset >> 32;
}
 
void tss_initialize(struct tss *t)
{
memsetb((__address) t, sizeof(struct tss), 0);
}
 
/*
* This function takes care of proper setup of IDT and IDTR.
*/
void idt_init(void)
{
struct idescriptor *d;
int i;
 
for (i = 0; i < IDT_ITEMS; i++) {
d = &idt[i];
 
d->unused = 0;
d->selector = idtselector(KTEXT_DES);
 
d->present = 1;
d->type = AR_INTERRUPT; /* masking interrupt */
 
if (i == VECTOR_SYSCALL) {
/*
* The syscall interrupt gate must be calleable from userland.
*/
d->dpl |= PL_USER;
}
idt_setoffset(d, ((__address) interrupt_handlers) + i*interrupt_handler_size);
trap_register(i, null_interrupt);
}
trap_register(13, gp_fault);
trap_register( 7, nm_fault);
trap_register(12, ss_fault);
}
 
 
/* Clean IOPL(12,13) and NT(14) flags in EFLAGS register */
static void clean_IOPL_NT_flags(void)
{
asm
(
"pushfq;"
"pop %%rax;"
"and $~(0x7000),%%rax;"
"pushq %%rax;"
"popfq;"
:
:
:"%rax"
);
}
 
/* Clean AM(18) flag in CR0 register */
static void clean_AM_flag(void)
{
asm
(
"mov %%cr0,%%rax;"
"and $~(0x40000),%%rax;"
"mov %%rax,%%cr0;"
:
:
:"%rax"
);
}
 
void pm_init(void)
{
struct descriptor *gdt_p = (struct descriptor *) PA2KA(gdtr.base);
struct tss_descriptor *tss_d;
 
/*
* Each CPU has its private GDT and TSS.
* All CPUs share one IDT.
*/
 
if (config.cpu_active == 1) {
idt_init();
/*
* NOTE: bootstrap CPU has statically allocated TSS, because
* the heap hasn't been initialized so far.
*/
tss_p = &tss;
}
else {
tss_p = (struct tss *) malloc(sizeof(struct tss));
if (!tss_p)
panic("could not allocate TSS\n");
}
 
tss_initialize(tss_p);
 
tss_d = (struct tss_descriptor *) &gdt_p[TSS_DES];
tss_d[TSS_DES].present = 1;
tss_d[TSS_DES].type = AR_TSS;
tss_d[TSS_DES].dpl = PL_KERNEL;
gdt_tss_setbase(&gdt_p[TSS_DES], (__address) tss_p);
gdt_tss_setlimit(&gdt_p[TSS_DES], sizeof(struct tss) - 1);
 
/*
* As of this moment, the current CPU has its own GDT pointing
* to its own TSS. We just need to load the TR register.
*/
__asm__("ltr %0" : : "r" ((__u16) gdtselector(TSS_DES)));
clean_IOPL_NT_flags(); /* Disable I/O on nonprivileged levels */
clean_AM_flag(); /* Disable alignment check */
}