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Ignore whitespace Rev 219 → Rev 224

/SPARTAN/trunk/arch/amd64/include/pm.h
86,16 → 86,16
unsigned base_0_15: 16;
unsigned base_16_23: 8;
unsigned type: 4;
unsigned reserve1 : 1;
unsigned : 1;
unsigned dpl : 2;
unsigned present : 1;
unsigned limit_16_19: 4;
unsigned available: 1;
unsigned reserve2: 2;
unsigned : 2;
unsigned granularity : 1;
unsigned base_24_31: 8;
unsigned base_32_63 : 32;
unsigned reserve3 : 32;
unsigned : 32;
} __attribute__ ((packed));
 
struct idescriptor {
107,8 → 107,8
unsigned dpl: 2;
unsigned present : 1;
unsigned offset_16_31: 16;
unsigned offset_32_63: 16;
unsigned reserved : 32;
unsigned offset_32_63: 32;
unsigned : 32;
} __attribute__ ((packed));
 
struct ptr_16_64 {
/SPARTAN/trunk/arch/amd64/include/asm.h
36,7 → 36,6
void asm_delay_loop(__u32 t);
void asm_fake_loop(__u32 t);
 
 
/* TODO: implement the real stuff */
static inline __address get_stack_base(void)
{
44,6 → 43,7
}
 
static inline void cpu_sleep(void) { __asm__("hlt"); };
static inline void cpu_halt(void) { __asm__("hlt"); };
 
 
static inline __u8 inb(__u16 port)
137,7 → 137,7
*
* @return Value read.
*/
static inline __u32 read_cr2(void) { __u64 v; __asm__ volatile ("movq %%cr2,%0" : "=r" (v)); return v; }
static inline __u64 read_cr2(void) { __u64 v; __asm__ volatile ("movq %%cr2,%0" : "=r" (v)); return v; }
 
/** Write CR3
*
153,16 → 153,9
*
* @return Value read.
*/
static inline __u32 read_cr3(void) { __u64 v; __asm__ volatile ("movq %%cr3,%0" : "=r" (v)); return v; }
static inline __u64 read_cr3(void) { __u64 v; __asm__ volatile ("movq %%cr3,%0" : "=r" (v)); return v; }
 
/** Set priority level low
*
* Enable interrupts and return previous
* value of EFLAGS.
*/
 
 
 
extern size_t interrupt_handler_size;
extern void interrupt_handlers(void);