/SPARTAN/trunk/arch/ppc/include/cpu.h |
---|
31,8 → 31,6 |
#include <typedefs.h> |
#define CPU_ID_ARCH 0 |
struct cpu_arch { |
}; |
/SPARTAN/trunk/arch/ia64/include/cpu.h |
---|
31,8 → 31,6 |
#include <typedefs.h> |
#define CPU_ID_ARCH 0 |
struct cpu_arch { |
}; |
/SPARTAN/trunk/arch/mips/include/cpu.h |
---|
29,8 → 29,6 |
#ifndef __mips_CPU_H__ |
#define __mips_CPU_H__ |
#define CPU_ID_ARCH 0 |
struct cpu_arch { |
int imp_num; |
int rev_num; |
/SPARTAN/trunk/arch/amd64/include/cpu.h |
---|
35,12 → 35,6 |
#include <arch/pm.h> |
#include <arch/asm.h> |
#ifdef __SMP__ |
#define CPU_ID_ARCH (read_dr0()) |
#else |
#define CPU_ID_ARCH (0) |
#endif |
struct cpu_arch { |
int vendor; |
int family; |
/SPARTAN/trunk/arch/ia32/include/asm.h |
---|
83,22 → 83,6 |
*/ |
static inline __u32 read_cr3(void) { __u32 v; __asm__ volatile ("movl %%cr3,%0" : "=r" (v)); return v; } |
/** Write DR0 |
* |
* Write value to DR0. |
* |
* @param v Value to be written. |
*/ |
static inline void write_dr0(__u32 v) { __asm__ volatile ("movl %0,%%dr0\n" : : "r" (v)); } |
/** Read DR0 |
* |
* Return value in DR0 |
* |
* @return Value read. |
*/ |
static inline __u32 read_dr0(void) { __u32 v; __asm__ volatile ("movl %%dr0,%0" : "=r" (v)); return v; } |
/** Set priority level low |
* |
* Enable interrupts and return previous |
/SPARTAN/trunk/arch/ia32/include/cpu.h |
---|
33,12 → 33,6 |
#include <arch/pm.h> |
#include <arch/asm.h> |
#ifdef __SMP__ |
#define CPU_ID_ARCH (read_dr0()) |
#else |
#define CPU_ID_ARCH (0) |
#endif |
struct cpu_arch { |
int vendor; |
int family; |
/SPARTAN/trunk/arch/ia32/src/ia32.c |
---|
51,8 → 51,6 |
{ |
pm_init(); |
write_dr0(config.cpu_active - 1); |
if (config.cpu_active == 1) { |
bios_init(); |
i8042_init(); /* a20 bit */ |