/SPARTAN/trunk/arch/ia64/include/asm.h |
---|
31,6 → 31,7 |
#include <arch/types.h> |
#include <config.h> |
#include <arch/register.h> |
/** Return base address of current stack |
* |
47,25 → 48,163 |
return v; |
} |
/** Read IVR (External Interrupt Vector Register) |
/** Read IVR (External Interrupt Vector Register). |
* |
* @return Highest priority, pending, unmasked external interrupt vector. |
*/ |
static inline __u8 read_ivr(void) |
static inline __u64 ivr_read(void) |
{ |
__u64 v; |
__asm__ volatile ("mov %0 = cr65\n" : "=r" (v)); |
__asm__ volatile ("mov %0 = cr.ivr\n" : "=r" (v)); |
return (__u8) (v & 0xf); |
return v; |
} |
/** Write ITC (Interval Timer Counter) register. |
* |
* @param New counter value. |
*/ |
static inline void itc_write(__u64 v) |
{ |
__asm__ volatile ("mov ar.itc = %0\n" : : "r" (v)); |
} |
void cpu_sleep(void); |
/** Read ITC (Interval Timer Counter) register. |
* |
* @return Current counter value. |
*/ |
static inline __u64 itc_read(void) |
{ |
__u64 v; |
void asm_delay_loop(__u32 t); |
__asm__ volatile ("mov %0 = ar.itc\n" : "=r" (v)); |
return v; |
} |
/** Write ITM (Interval Timer Match) register. |
* |
* @param New match value. |
*/ |
static inline void itm_write(__u64 v) |
{ |
__asm__ volatile ("mov cr.itm = %0\n" : : "r" (v)); |
} |
/** Write ITV (Interval Timer Vector) register. |
* |
* @param New vector and masked bit. |
*/ |
static inline void itv_write(__u64 v) |
{ |
__asm__ volatile ("mov cr.itv = %0\n" : : "r" (v)); |
} |
/** Write EOI (End Of Interrupt) register. |
* |
* @param This value is ignored. |
*/ |
static inline void eoi_write(__u64 v) |
{ |
__asm__ volatile ("mov cr.eoi = %0\n" : : "r" (v)); |
} |
/** Read TPR (Task Priority Register). |
* |
* @return Current value of TPR. |
*/ |
static inline __u64 tpr_read(void) |
{ |
__u64 v; |
__asm__ volatile ("mov %0 = cr.tpr\n" : "=r" (v)); |
return v; |
} |
/** Write TPR (Task Priority Register). |
* |
* @param New value of TPR. |
*/ |
static inline void tpr_write(__u64 v) |
{ |
__asm__ volatile ("mov cr.tpr = %0\n" : : "r" (v)); |
} |
/** Disable interrupts. |
* |
* Disable interrupts and return previous |
* value of PSR. |
* |
* @return Old interrupt priority level. |
*/ |
static ipl_t interrupts_disable(void) |
{ |
__u64 v; |
__asm__ volatile ( |
"mov %0 = psr\n" |
"rsm %1\n" |
: "=r" (v) |
: "i" (PSR_I_MASK) |
); |
return (ipl_t) v; |
} |
/** Enable interrupts. |
* |
* Enable interrupts and return previous |
* value of PSR. |
* |
* @return Old interrupt priority level. |
*/ |
static ipl_t interrupts_enable(void) |
{ |
__u64 v; |
__asm__ volatile ( |
"mov %0 = psr\n" |
"ssm %1\n" |
";;\n" |
"srlz.d\n" |
: "=r" (v) |
: "i" (PSR_I_MASK) |
); |
return (ipl_t) v; |
} |
/** Restore interrupt priority level. |
* |
* Restore PSR. |
* |
* @param ipl Saved interrupt priority level. |
*/ |
static inline void interrupts_restore(ipl_t ipl) |
{ |
__asm__ volatile ( |
"mov psr.l = %0\n" |
";;\n" |
"srlz.d\n" |
: : "r" ((__u64) ipl) |
); |
} |
/** Return interrupt priority level. |
* |
* @return PSR. |
*/ |
static inline ipl_t interrupts_read(void) |
{ |
__u64 v; |
__asm__ volatile ("mov %0 = psr\n" : "=r" (v)); |
return (ipl_t) v; |
} |
#define set_shadow_register(reg,val) {__u64 v = val; __asm__ volatile("mov r15 = %0;;\n""bsw.0;;\n""mov " #reg " = r15;;\n""bsw.1;;\n" : : "r" (v) : "r15" ); } |
#define get_shadow_register(reg,val) {__u64 v ; __asm__ volatile("bsw.0;;\n" "mov r15 = r" #reg ";;\n" "bsw.1;;\n" "mov %0 = r15;;\n" : "=r" (v) : : "r15" ); val=v; } |
73,10 → 212,8 |
#define get_aplication_register(reg,val) {__u64 v ; __asm__ volatile("mov r15 = ar" #reg ";;\n" "mov %0 = r15;;\n" : "=r" (v) : : "r15" ); val=v; } |
#define get_psr(val) {__u64 v ; __asm__ volatile("mov r15 = psr;;\n" "mov %0 = r15;;\n" : "=r" (v) : : "r15" ); val=v; } |
extern void cpu_halt(void); |
extern void cpu_sleep(void); |
extern void asm_delay_loop(__u32 t); |
void cpu_halt(void); |
#endif |
/SPARTAN/trunk/arch/ia64/include/register.h |
---|
0,0 → 1,38 |
/* |
* Copyright (C) 2005 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
#ifndef __ia64_REGISTER_H__ |
#define __ia64_REGISTER_H__ |
#include <arch/types.h> |
#define CR_IVR_MASK 0xf |
#define PSR_I_MASK 0x4000 |
#endif |
/SPARTAN/trunk/arch/ia64/include/barrier.h |
---|
32,14 → 32,14 |
/* |
* TODO: Implement true IA-64 memory barriers for macros below. |
*/ |
#define CS_ENTER_BARRIER() __asm__ volatile ("" ::: "memory") |
#define CS_LEAVE_BARRIER() __asm__ volatile ("" ::: "memory") |
#define CS_ENTER_BARRIER() memory_barrier() |
#define CS_LEAVE_BARRIER() memory_barrier() |
#define memory_barrier() |
#define read_barrier() |
#define write_barrier() |
#define memory_barrier() __asm__ volatile ("mf\n" ::: "memory") |
#define read_barrier() memory_barrier() |
#define write_barrier() memory_barrier() |
#define srlz_i() __asm__ volatile (";; srlz.i ;;\n" ::: "memory") |
#define srlz_d() __asm__ volatile (";; srlz.d ;;\n" ::: "memory") |
#define srlz_d() __asm__ volatile (";; srlz.d\n" ::: "memory") |
#endif |
/SPARTAN/trunk/arch/ia64/src/dummy.s |
---|
35,10 → 35,6 |
.global arch_late_init |
.global cpu_identify |
.global cpu_print_report |
.global interrupts_disable |
.global interrupts_enable |
.global interrupts_read |
.global interrupts_restore |
.global cpu_sleep |
.global dummy |
.global fpu_enable |
52,10 → 48,6 |
arch_late_init: |
cpu_identify: |
cpu_print_report: |
interrupts_disable: |
interrupts_enable: |
interrupts_read: |
interrupts_restore: |
cpu_sleep: |
fpu_init: |
fpu_enable: |
/SPARTAN/trunk/arch/ia64/src/interrupt.c |
---|
32,6 → 32,7 |
#include <arch/types.h> |
#include <arch/asm.h> |
#include <arch/barrier.h> |
#include <arch/register.h> |
void external_interrupt(void) |
{ |
38,7 → 39,7 |
__u8 ivr; |
srlz_d(); |
ivr = read_ivr(); |
ivr = ivr_read() & CR_IVR_MASK; |
srlz_d(); |
switch(ivr) { |
/SPARTAN/trunk/arch/ia32/include/asm.h |
---|
138,7 → 138,8 |
* |
* @return Old interrupt priority level. |
*/ |
static inline ipl_t interrupts_enable(void) { |
static inline ipl_t interrupts_enable(void) |
{ |
ipl_t v; |
__asm__ volatile ( |
"pushf\n\t" |
156,7 → 157,8 |
* |
* @return Old interrupt priority level. |
*/ |
static inline ipl_t interrupts_disable(void) { |
static inline ipl_t interrupts_disable(void) |
{ |
ipl_t v; |
__asm__ volatile ( |
"pushf\n\t" |
173,7 → 175,8 |
* |
* @param ipl Saved interrupt priority level. |
*/ |
static inline void interrupts_restore(ipl_t ipl) { |
static inline void interrupts_restore(ipl_t ipl) |
{ |
__asm__ volatile ( |
"pushl %0\n\t" |
"popf\n" |
185,7 → 188,8 |
* |
* @return EFLAFS. |
*/ |
static inline ipl_t interrupts_read(void) { |
static inline ipl_t interrupts_read(void) |
{ |
ipl_t v; |
__asm__ volatile ( |
"pushf\n\t" |