| /SPARTAN/trunk/arch/mips/boot/boot.S |
|---|
| 35,7 → 35,7 |
| #include <arch/asm/boot.h> |
| #ifndef KERNEL_LOAD_ADDRESS |
| # define KERNEL_LOAD_ADDRESS 0x80010000 |
| # define KERNEL_LOAD_ADDRESS 0x80100000 |
| #endif |
| .global start |
| /SPARTAN/trunk/arch/mips/include/cp0.h |
|---|
| 41,6 → 41,11 |
| #define cp0_status_im_shift 8 |
| #define cp0_status_im_mask 0xff00 |
| #define cp0_cause_excno(cause) ((cause >> 2) & 0x1f) |
| #define cp0_cause_coperr(cause) ((cause >> 28) & 0x3) |
| #define fpu_cop_id 1 |
| /* |
| * Magic value for use in msim. |
| * On AMD Duron 800Mhz, this roughly seems like one us. |
| /SPARTAN/trunk/arch/mips/Makefile.inc |
|---|
| 28,13 → 28,13 |
| ifeq (${MACHINE},lgxemul) |
| CFLAGS += -DHAVE_FPU -DFPU_LAZY -mips3 |
| BFD = ecoff-littlemips |
| KERNEL_LOAD_ADDRESS = 0x80010000 |
| KERNEL_LOAD_ADDRESS = 0x80100000 |
| endif |
| ifeq (${MACHINE},bgxemul) |
| CFLAGS += -EB -mmemcpy -DBIG_ENDIAN -DHAVE_FPU -DFPU_LAZY -mips3 |
| BFD = ecoff-bigmips |
| KERNEL_LOAD_ADDRESS = 0x80010000 |
| KERNEL_LOAD_ADDRESS = 0x80100000 |
| endif |
| # MSIM needs lwl/swl patch & 4kc instruction patch to work |
| 42,7 → 42,7 |
| ifeq (${MACHINE},msim) |
| BFD = binary |
| CFLAGS += -msoft-float -march=4kc |
| KERNEL_LOAD_ADDRESS = 0x80010000 |
| KERNEL_LOAD_ADDRESS = 0x80100000 |
| endif |
| # SIMICS 4kc emulation is broken, although for instructions |
| 50,7 → 50,7 |
| ifeq (${MACHINE},simics) |
| BFD = elf32-little |
| CFLAGS += -msoft-float -mips3 |
| KERNEL_LOAD_ADDRESS = 0x80010000 |
| KERNEL_LOAD_ADDRESS = 0x80100000 |
| endif |
| ../arch/$(ARCH)/_link.ld: ../arch/$(ARCH)/_link.ld.in |
| /SPARTAN/trunk/arch/mips/src/exception.c |
|---|
| 36,6 → 36,7 |
| void exception(struct exception_regdump *pstate) |
| { |
| int cause; |
| int excno; |
| __u32 epc_shift = 0; |
| 59,8 → 60,10 |
| if (THREAD && !THREAD->pstate) |
| THREAD->pstate = pstate; |
| cause = cp0_cause_read(); |
| excno = cp0_cause_excno(cause); |
| /* decode exception number and process the exception */ |
| switch (excno = (cp0_cause_read() >> 2) & 0x1f) { |
| switch (excno) { |
| case EXC_Int: |
| interrupt(); |
| break; |
| 70,10 → 73,11 |
| break; |
| case EXC_CpU: |
| #ifdef FPU_LAZY |
| scheduler_fpu_lazy_request(); |
| #else |
| panic("unhandled Coprocessor Unusable Exception\n"); |
| if (cp0_cause_coperr(cause) == fpu_cop_id) |
| scheduler_fpu_lazy_request(); |
| else |
| #endif |
| panic("unhandled Coprocessor Unusable Exception\n"); |
| break; |
| case EXC_Mod: |
| panic("unhandled TLB Modification Exception\n"); |
| /SPARTAN/trunk/arch/mips/src/mips.c |
|---|
| 37,6 → 37,8 |
| #include <memstr.h> |
| #include <arch/interrupt.h> |
| #include <print.h> |
| /* Size of the code jumping to the exception handler code |
| * - J+NOP |
| */ |
| 46,9 → 48,6 |
| #define NORM_EXC ((char *) 0x80000180) |
| #define CACHE_EXC ((char *) 0x80000100) |
| #include <arch/debug.h> |
| #include <print.h> |
| void arch_pre_mm_init(void) |
| { |
| /* It is not assumed by default */ |