| /SPARTAN/trunk/doc/TODO |
|---|
| 10,11 → 10,11 |
| + get user mode support for all architectures |
| + save/restore floating point context on context switch |
| + [ia32] lazy context switch using TS flag [DONE] |
| + [ia32] lazy context switch using TS flag [DONE] |
| + [ia32] MMX,SSE1-.. initialization |
| + [ia32] review privilege separation |
| + zero IOPL in EFLAGS |
| + before IRET (from SYSCALL), zero NT in EFLAGS |
| + zero IOPL in EFLAGS [DONE] |
| + before IRET (from SYSCALL), zero NT in EFLAGS [DONE] |
| + [ia32] review the cache controling bits in CR0 register |
| + [ia32] zero the alignment exception bit in EFLAGS |
| + make emulated architectures also work on real hardware |
| /SPARTAN/trunk/arch/ia32/src/asm.S |
|---|
| 116,6 → 116,15 |
| pop %ds |
| # CLNT |
| pushfl; |
| pop %eax; |
| and $0xFFFFBFFF; |
| push %eax; |
| popfl; |
| # Test if this is interrupt with error word or not |
| mov $\i,%cl; |
| movl $1,%eax; |
| /SPARTAN/trunk/arch/ia32/src/cpu/cpu.c |
|---|
| 49,6 → 49,7 |
| #define INTEL_CPUID_ECX 0x6c65746e |
| #define INTEL_CPUID_EDX 0x49656e69 |
| enum vendor { |
| VendorUnknown=0, |
| VendorAMD, |
| 89,6 → 90,7 |
| void cpu_arch_init(void) |
| { |
| CPU->arch.tss = tss_p; |
| /SPARTAN/trunk/arch/ia32/src/pm.c |
|---|
| 128,6 → 128,25 |
| } |
| static void clean_IOPL_NT_flags(void) |
| { |
| asm |
| ( |
| "pushfl;" |
| "pop %%eax;" |
| "and $0xffff8fff,%%eax;" |
| "push %%eax;" |
| "popfl;" |
| : |
| : |
| :"%eax" |
| ); |
| } |
| void pm_init(void) |
| { |
| struct descriptor *gdt_p = (struct descriptor *) PA2KA(gdtr.base); |
| 165,4 → 184,6 |
| * to its own TSS. We just need to load the TR register. |
| */ |
| __asm__("ltr %0" : : "r" ((__u16) selector(TSS_DES))); |
| clean_IOPL_NT_flags(); |
| } |
| /SPARTAN/trunk/arch/ia32/src/userspace.c |
|---|
| 46,6 → 46,13 |
| pri = cpu_priority_high(); |
| __asm__ volatile ("" |
| // CLNT |
| "pushfl;" |
| "pop %%eax;" |
| "and $0xFFFFBFFF;" |
| "push %%eax;" |
| "popfl;" |
| "pushl %0\n" |
| "pushl %1\n" |
| "pushl %2\n" |