/kernel/trunk/arch/sparc64/include/asm.h |
---|
56,7 → 56,51 |
__asm__ volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0)); |
} |
/** Read TICK_compare Register. |
* |
* @return Value of TICK_comapre register. |
*/ |
static inline __u64 tick_compare_read(void) |
{ |
__u64 v; |
__asm__ volatile ("rd %%tick_cmpr, %0\n" : "=r" (v)); |
return v; |
} |
/** Write TICK_compare Register. |
* |
* @param New value of TICK_comapre register. |
*/ |
static inline void tick_compare_write(__u64 v) |
{ |
__asm__ volatile ("wr %0, %1, %%tick_cmpr\n" : : "r" (v), "i" (0)); |
} |
/** Read TICK Register. |
* |
* @return Value of TICK register. |
*/ |
static inline __u64 tick_read(void) |
{ |
__u64 v; |
__asm__ volatile ("rdpr %%tick, %0\n" : "=r" (v)); |
return v; |
} |
/** Write TICK Register. |
* |
* @param New value of TICK register. |
*/ |
static inline void tick_write(__u64 v) |
{ |
__asm__ volatile ("wrpr %0, %1, %%tick\n" : : "r" (v), "i" (0)); |
} |
/** Enable interrupts. |
* |
* Enable interrupts and return previous |
196,6 → 240,8 |
__asm__ volatile ("stxa %0, [%1] %2\n" : : "r" (v), "r" (va), "i" (asi) : "memory"); |
} |
void cpu_halt(void); |
void cpu_sleep(void); |
void asm_delay_loop(__u32 t); |
/kernel/trunk/arch/sparc64/include/mm/mmu.h |
---|
103,7 → 103,7 |
#define dmmu_disable() dmmu_set(false) |
/** Disable or Enable IMMU. */ |
static inline immu_set(bool enable) |
static inline void immu_set(bool enable) |
{ |
lsu_cr_reg_t cr; |
114,7 → 114,7 |
} |
/** Disable or Enable DMMU. */ |
static inline dmmu_set(bool enable) |
static inline void dmmu_set(bool enable) |
{ |
lsu_cr_reg_t cr; |
/kernel/trunk/arch/sparc64/include/mm/tlb.h |
---|
114,7 → 114,7 |
* @param entry TLB Entry index. |
* @param value Value to be written. |
*/ |
static inline __u64 itlb_data_access_write(index_t entry, __u64 value) |
static inline void itlb_data_access_write(index_t entry, __u64 value) |
{ |
tlb_data_access_addr_t reg; |
144,7 → 144,7 |
* @param entry TLB Entry index. |
* @param value Value to be written. |
*/ |
static inline __u64 dtlb_data_access_write(index_t entry, __u64 value) |
static inline void dtlb_data_access_write(index_t entry, __u64 value) |
{ |
tlb_data_access_addr_t reg; |
/kernel/trunk/arch/sparc64/include/register.h |
---|
36,7 → 36,7 |
__u64 value; |
struct { |
__u16 manuf; /**< Manufacturer code. */ |
__u16 impl; |
__u16 impl; /**< Implementation code. */ |
__u8 mask; /**< Mask set revision. */ |
unsigned : 8; |
__u8 maxtl; |
66,4 → 66,24 |
}; |
typedef union pstate_reg pstate_reg_t; |
/** TICK Register. */ |
union tick_reg { |
__u64 value; |
struct { |
unsigned npt : 1; /**< Non-privileged Trap enable. */ |
__u64 counter : 63; /**< Elapsed CPU clck cycle counter. */ |
} __attribute__ ((packed)); |
}; |
typedef union tick_reg tick_reg_t; |
/** TICK_compare Register. */ |
union tick_compare_reg { |
__u64 value; |
struct { |
unsigned int_dis : 1; /**< TICK_INT interrupt enable. */ |
__u64 tick_cmpr : 63; /**< Compare value for TICK interrupts. */ |
} __attribute__ ((packed)); |
}; |
typedef union tick_compare_reg tick_compare_reg_t; |
#endif |