154,7 → 154,9 |
( (p->access_permission_0 == PTE_AP_USER_RO_KERNEL_RW) << PAGE_READ_SHIFT ) | |
( (p->access_permission_0 == PTE_AP_USER_RW_KERNEL_RW) << PAGE_READ_SHIFT ) | |
( (p->access_permission_0 == PTE_AP_USER_RW_KERNEL_RW) << PAGE_WRITE_SHIFT ) | |
( (p->access_permission_0 != PTE_AP_USER_NO_KERNEL_RW) << PAGE_USER_SHIFT ) | |
( (p->access_permission_0 != PTE_AP_USER_NO_KERNEL_RW) << PAGE_USER_SHIFT ) | |
( (p->access_permission_0 == PTE_AP_USER_NO_KERNEL_RW) << PAGE_READ_SHIFT ) | |
( (p->access_permission_0 == PTE_AP_USER_NO_KERNEL_RW) << PAGE_WRITE_SHIFT ) | |
( 1 << PAGE_EXEC_SHIFT ) | |
( p->bufferable << PAGE_CACHEABLE ) |
; |
175,10 → 177,13 |
|
if (flags & PAGE_NOT_PRESENT) { |
p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT; |
// p->should_be_zero = 1; |
p->should_be_zero = 1; |
// TODO: remove in final version |
// For Michal: Have to be here ... ensures this entry contains at least 1 non zero bit |
// all zero bits signals PTE_VALID_ARCH , it's different from not_present |
} else { |
p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE; |
// p->should_be_zero = 0; |
p->should_be_zero = 0; |
} |
} |
|
199,10 → 204,10 |
|
if (flags & PAGE_NOT_PRESENT) { |
p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT; |
// p->access_permission_3 = 1; |
p->access_permission_3 = 1; |
} else { |
p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE; |
// p->access_permission_3 = p->access_permission_0; |
p->access_permission_3 = p->access_permission_0; |
} |
|
p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0; |