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Ignore whitespace Rev 2146 → Rev 2147

/branches/arm/kernel/arch/arm32/include/types.h
70,9 → 70,49
 
/** Page Table Entry. */
typedef struct {
/* placeholder */
/**PageTables are so different that we have different types
* for level 0 and level1 page table entries
*/
unsigned dummy : 32;
} pte_t;
 
typedef struct {
unsigned destriptor_type : 2;
unsigned machine_depend : 3; // Alf: ???? v Architecture previev neni vyznam definovan
unsigned domain : 4;
unsigned should_be_zero : 1:
unsigned coarse_table_addr : 22;
} __attribute__ ((packed)) pte_level0_t;
 
//TODO Alf: Comments
typedef struct {
unsigned destriptor_type : 2;
unsigned bufferable : 1;
unsigned cacheable : 1;
unsigned access_permission_0 : 2;
unsigned access_permission_1 : 2;
unsigned access_permission_2 : 2;
unsigned access_permission_3 : 2;
unsigned frame_base_addr : 20;
} __attribute__ ((packed)) pte__level1_t;
 
/// Page table level 1 access permission constants
/// User no acess, kernel no access
#define pte_ap_user_no_kernel_no 0
/// User no acess, kernel read/write
#define pte_ap_user_no_kernel_rw 1
/// User read only, kernel read/write
#define pte_ap_user_ro_kernel_rw 2
/// User read/write, kernel read/write
#define pte_ap_user_rw_kernel_rw 2
 
/// Value of descriptor_type in pte_level0_t and pte_level1_t that signal not present flag
#define pte_descriptor_not_preset 0
/// Value of descriptor_type in pte_level0_t that signal a coarse page table format
#define pte_descriptor_coarse_table 1
/// Value of descriptor_type in pte_level1_t that signal a small page table entry format
#define pte_descriptor_small_page 2
 
#endif
 
/** @}
/branches/arm/kernel/arch/arm32/include/mm/page.h
51,61 → 51,129
#endif
 
#ifdef KERNEL
// Using small pages <==> 4kb
#define PTL0_ENTRIES_ARCH (2<<12) // 4096
#define PTL1_ENTRIES_ARCH 0
#define PTL2_ENTRIES_ARCH 0
#define PTL3_ENTRIES_ARCH (2<<8) // 256
 
#define PTL0_ENTRIES_ARCH 0 /* TODO */
#define PTL1_ENTRIES_ARCH 0 /* TODO */
#define PTL2_ENTRIES_ARCH 0 /* TODO */
#define PTL3_ENTRIES_ARCH 0 /* TODO */
#define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 20) & 0xfff)
#define PTL1_INDEX_ARCH(vaddr) 0
#define PTL2_INDEX_ARCH(vaddr) 0
#define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x0ff)
 
#define PTL0_INDEX_ARCH(vaddr) 0 /* TODO */
#define PTL1_INDEX_ARCH(vaddr) 0 /* TODO */
#define PTL2_INDEX_ARCH(vaddr) 0 /* TODO */
#define PTL3_INDEX_ARCH(vaddr) 0 /* TODO */
 
#define SET_PTL0_ADDRESS_ARCH(ptl0)
#define GET_PTL1_ADDRESS_ARCH(ptl0, i) ((pte_t *)( (((pte_level0_t*)(ptl0))[(i)]) & 0xfffffc00 )
#define GET_PTL2_ADDRESS_ARCH(ptl1, i) (ptl1)
#define GET_PTL3_ADDRESS_ARCH(ptl2, i) (ptl2)
#define GET_FRAME_ADDRESS_ARCH(ptl3, i) ( (uintptr_t)(((pte_level1_t*)(ptl3))[(i)]) & 0xfffff000 )
 
#define GET_PTL1_ADDRESS_ARCH(ptl0, i) 0 /* TODO */
#define GET_PTL2_ADDRESS_ARCH(ptl1, i) 0 /* TODO */
#define GET_PTL3_ADDRESS_ARCH(ptl2, i) 0 /* TODO */
#define GET_FRAME_ADDRESS_ARCH(ptl3, i) 0 /* TODO */
#define SET_PTL0_ADDRESS_ARCH(ptl0) // TODO
#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) (((pte_level0_t *)(ptl0))[(i)].coarse_table_addr = (a)>>10)
#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) (((pte_level1_t *)(ptl3))[(i)].frame_base_addr = (a)>>12)
 
#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) /* TODO */
#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a) /* TODO */
#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a) /* TODO */
#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) /* TODO */
#define GET_PTL1_FLAGS_ARCH(ptl0, i) get_pt_level0_flags((pte_level0_t *)(ptl0), (index_t)(i))
#define GET_PTL2_FLAGS_ARCH(ptl1, i) PAGE_PRESENT
#define GET_PTL3_FLAGS_ARCH(ptl2, i) PAGE_PRESENT
#define GET_FRAME_FLAGS_ARCH(ptl3, i) get_pt_level1_flags((pte_level1_t *)(ptl3), (index_t)(i))
 
#define GET_PTL1_FLAGS_ARCH(ptl0, i) 0 /* TODO */
#define GET_PTL2_FLAGS_ARCH(ptl1, i) 0 /* TODO */
#define GET_PTL3_FLAGS_ARCH(ptl2, i) 0 /* TODO */
#define GET_FRAME_FLAGS_ARCH(ptl3, i) 0 /* TODO */
#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) set_pt_level0_flags((pte_level0_t *)(ptl0), (index_t)(i), (x))
#define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
#define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) set_pt_level1_flags((pte_level1t *)(ptl3), (index_t)(i), (x))
 
#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) /* TODO */
#define SET_PTL2_FLAGS_ARCH(ptl1, i, x) /* TODO */
#define SET_PTL3_FLAGS_ARCH(ptl2, i, x) /* TODO */
#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) /* TODO */
#define PTE_VALID_ARCH(pte) (*((uint32_t *) (pte)) != 0)
#define PTE_PRESENT_ARCH(pte) ( ((pte_level0_t *)(pte))->descriptor_type )
#define PTE_GET_FRAME_ARCH(pte) ( ((pte_level1_t *)(pte))->frame_base_addr << FRAME_WIDTH) // pte should point into ptl3
#define PTE_WRITABLE_ARCH(pte) ( ((pte_level1_t *)(pte))->access_permission_0 == pte_ap_user_rw_kernel_rw ) // pte should point into ptl3
#define PTE_EXECUTABLE_ARCH(pte) 1
 
#define PTE_VALID_ARCH(pte) 0 /* TODO */
#define PTE_PRESENT_ARCH(pte) 0 /* TODO */
#define PTE_GET_FRAME_ARCH(pte) 0 /* TODO */
#define PTE_WRITABLE_ARCH(pte) 0 /* TODO */
#define PTE_EXECUTABLE_ARCH(pte) 0 /* TODO */
 
#ifndef __ASM__
 
#include <mm/mm.h>
#include <arch/exception.h>
 
static inline int get_pt_flags(pte_t *pt, index_t i)
//TODO Comment: Page table structure as in other architectures
static inline int get_pt_level0_flags(pte_level0_t *pt, index_t i)
{
return 0; /* TODO */
pte_level0_t *p = &pt[i];
 
return (
( p->destriptor_type != pte_descriptor_not_preset ) << PAGE_PRESENT_SHIFT |
( 1 << PAGE_READ_SHIFT ) |
( 1 << PAGE_EXEC_SHIFT ) |
( 1 << PAGE_CACHEABLE )
// Alf Note: MayBe return WriteAble because level0 should use only kernel which can write
// Alf Note: MayBe return global flag if index i > 2048 (horni 2GB because kernel is mapped globaly)
);
 
}
static inline int get_pt_level1_flags(pte_t *pt, index_t i)
{
pte_level1_t *p = &pt[i];
 
static inline void set_pt_flags(pte_t *pt, index_t i, int flags)
return (
( p->destriptor_type != pte_descriptor_not_preset ) << PAGE_PRESENT_SHIFT |
( (p->access_permission_0 == pte_ap_user_ro_kernel_rw) << PAGE_READ_SHIFT ) |
( (p->access_permission_0 == pte_ap_user_rw_kernel_rw) << PAGE_READ_SHIFT ) |
( (p->access_permission_0 == pte_ap_user_rw_kernel_rw) << PAGE_WRITE_SHIFT ) |
( (p->access_permission_0 != pte_ap_user_no_kernel_rw) << PAGE_USER_SHIFT ) |
( 1 << PAGE_EXEC_SHIFT ) |
( p->bufferable << PAGE_CACHEABLE )
// Alf Note: MayBe return global flag if index i > 2048 (horni 2GB because kernel is mapped globaly)
);
 
}
 
 
static inline void set_pt_level0_flags(pte_level0_t *pt, index_t i, int flags)
{
/* TODO */
pte_level0_t *p = &pt[i];
if ( flags & PAGE_NOT_PRESENT ) {
p->destriptor_type = pte_descriptor_not_preset;
p->should_be_zero = 1;
} else
{
p->destriptor_type = pte_descriptor_coarse_table;
p->should_be_zero = 0;
}
return;
}
 
/* We use same acess rights for whole page, so if page is set as not preset then
* in acess_rigts_3 set value 1
*/
static inline void set_pt_level1_flags(pte_level1_t *pt, index_t i, int flags)
{
pte_level1_t *p = &pt[i];
if ( flags & PAGE_NOT_PRESENT ) {
p->destriptor_type = pte_descriptor_not_preset;
p->access_permission_3 = 1; // Ensure not all bits set to zero ... correct acess rights are stored in other 0-2 access permission entries
} else
{
p->destriptor_type = pte_descriptor_coarse_table;
p->access_permission_3 = p->access_permission_0;
}
p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0;
// default kernel rw, user none
p->access_permission_0 = p->access_permission_1 = p->access_permission_2 = p->access_permission_3 = pte_ap_user_no_kernel_rw;
if ( flags & PAGE_USER ) {
if ( flags & PAGE_READ )
p->access_permission_0 = p->access_permission_1 = p->access_permission_2 = p->access_permission_3 = pte_ap_user_ro_kernel_rw;
if ( flags & PAGE_WRITE )
p->access_permission_0 = p->access_permission_1 = p->access_permission_2 = p->access_permission_3 = pte_ap_user_rw_kernel_rw;
}
return; return;
}
 
extern void page_arch_init(void);
 
#endif /* __ASM__ */
116,3 → 184,4
 
/** @}
*/