/trunk/kernel/doc/arch/sparc64 |
---|
6,3 → 6,19 |
The goal is to provide support for UltraSPARC |
implementation of SPARC V9 architecture. |
MACHINES |
o Sun Ultra 5 |
o Sun Enterprise E6500 (simulated) |
CPU |
o UltraSPARC II |
o UltraSPARC IIi |
SIMULATORS |
o simics 2.2.19, simics 3.0.17 |
TOOLCHAIN REQUIREMENTS |
o binutils 2.17 |
o gcc 4.1.1 |
o older versions may do as well, but are now obsoleted |
/trunk/kernel/genarch/include/kbd/z8530.h |
---|
37,10 → 37,13 |
#ifndef KERN_Z8530_H_ |
#define KERN_Z8530_H_ |
#define Z8530_INTRCV_DATA0 0x39 /* hardcoded for use in Simics */ |
extern void z8530_init(void); |
extern void z8530_poll(void); |
extern void z8530_grab(void); |
extern void z8530_release(void); |
extern void z8530_interrupt(void); |
#endif |
/trunk/kernel/genarch/src/kbd/z8530.c |
---|
38,8 → 38,8 |
#include <genarch/kbd/key.h> |
#include <genarch/kbd/scanc.h> |
#include <genarch/kbd/scanc_sun.h> |
#include <arch/drivers/fhc.h> |
#include <arch/drivers/z8530.h> |
#include <arch/drivers/kbd.h> |
#include <arch/interrupt.h> |
#include <cpu.h> |
#include <arch/asm.h> |
64,7 → 64,6 |
.read = key_read |
}; |
void z8530_interrupt(int n, istate_t *istate); |
void z8530_wait(void); |
/** Initialize keyboard and service interrupts using kernel routine */ |
71,13 → 70,12 |
void z8530_grab(void) |
{ |
} |
/** Resume the former interrupt vector */ |
void z8530_release(void) |
{ |
} |
#include <print.h> |
/** Initialize z8530. */ |
void z8530_init(void) |
{ |
84,13 → 82,22 |
chardev_initialize("z8530_kbd", &kbrd, &ops); |
stdin = &kbrd; |
(void) z8530_read_a(RR8); |
z8530_write_a(WR1, WR1_IARCSC); /* interrupt on all characters */ |
z8530_write_a(WR2, 12); /* FIXME: IRQ12 ??? */ |
/* 8 bits per character and enable receiver */ |
z8530_write_a(WR3, WR3_RX8BITSCH | WR3_RX_ENABLE); |
z8530_write_a(WR9, WR9_MIE); /* Master Interrupt Enable. */ |
/* |
* We need to initialize the FireHose Controller, |
* to which is this z8530 attached. Otherwise |
* interrupts generated by the z8530 would not |
* be forwarded to the CPU. |
*/ |
fhc_init(); |
} |
/** Process z8530 interrupt. |
98,8 → 105,9 |
* @param n Interrupt vector. |
* @param istate Interrupted state. |
*/ |
void z8530_interrupt(int n, istate_t *istate) |
void z8530_interrupt(void) |
{ |
z8530_poll(); |
} |
/** Wait until the controller reads its data. */ |
/trunk/kernel/arch/sparc64/include/asm.h |
---|
139,6 → 139,17 |
__asm__ volatile ("wr %0, %1, %%clear_softint\n" : : "r" (v), "i" (0)); |
} |
/** Write SET_SOFTINT Register. |
* |
* Bits set in SET_SOFTINT register will be set in SOFTINT register. |
* |
* @param v New value of SET_SOFTINT register. |
*/ |
static inline void set_softint_write(uint64_t v) |
{ |
__asm__ volatile ("wr %0, %1, %%set_softint\n" : : "r" (v), "i" (0)); |
} |
/** Enable interrupts. |
* |
* Enable interrupts and return previous |
/trunk/kernel/arch/sparc64/include/trap/interrupt.h |
---|
40,6 → 40,22 |
#include <arch/trap/trap_table.h> |
#include <arch/stack.h> |
/* Interrupt ASI registers. */ |
#define ASI_UDB_INTR_W 0x77 |
#define ASI_INTR_DISPATCH_STATUS 0x48 |
#define ASI_UDB_INTR_R 0x7f |
#define ASI_INTR_RECEIVE 0x49 |
/* VA's used with ASI_UDB_INTR_W register. */ |
#define ASI_UDB_INTR_W_DATA_0 0x40 |
#define ASI_UDB_INTR_W_DATA_1 0x50 |
#define ASI_UDB_INTR_W_DATA_2 0x60 |
/* VA's used with ASI_UDB_INTR_R register. */ |
#define ASI_UDB_INTR_R_DATA_0 0x40 |
#define ASI_UDB_INTR_R_DATA_1 0x50 |
#define ASI_UDB_INTR_R_DATA_2 0x60 |
#define TT_INTERRUPT_LEVEL_1 0x41 |
#define TT_INTERRUPT_LEVEL_2 0x42 |
#define TT_INTERRUPT_LEVEL_3 0x43 |
70,10 → 86,17 |
.endm |
.macro INTERRUPT_VECTOR_TRAP_HANDLER |
save %sp, -STACK_WINDOW_SAVE_AREA_SIZE, %sp |
SIMPLE_HANDLER interrupt |
restore |
retry |
.endm |
#endif /* __ASM__ */ |
#ifndef __ASM__ |
extern void interrupt(void); |
#endif /* !def __ASM__ */ |
#endif |
/** @} |
/trunk/kernel/arch/sparc64/include/mm/mmu.h |
---|
35,10 → 35,10 |
#ifndef __sparc64_MMU_H__ |
#define __sparc64_MMU_H__ |
/** LSU Control Register ASI. */ |
/* LSU Control Register ASI. */ |
#define ASI_LSU_CONTROL_REG 0x45 /**< Load/Store Unit Control Register. */ |
/** I-MMU ASIs. */ |
/* I-MMU ASIs. */ |
#define ASI_IMMU 0x50 |
#define ASI_IMMU_TSB_8KB_PTR_REG 0x51 |
#define ASI_IMMU_TSB_64KB_PTR_REG 0x52 |
47,13 → 47,13 |
#define ASI_ITLB_TAG_READ_REG 0x56 |
#define ASI_IMMU_DEMAP 0x57 |
/** Virtual Addresses within ASI_IMMU. */ |
/* Virtual Addresses within ASI_IMMU. */ |
#define VA_IMMU_TAG_TARGET 0x0 /**< IMMU tag target register. */ |
#define VA_IMMU_SFSR 0x18 /**< IMMU sync fault status register. */ |
#define VA_IMMU_TSB_BASE 0x28 /**< IMMU TSB base register. */ |
#define VA_IMMU_TAG_ACCESS 0x30 /**< IMMU TLB tag access register. */ |
/** D-MMU ASIs. */ |
/* D-MMU ASIs. */ |
#define ASI_DMMU 0x58 |
#define ASI_DMMU_TSB_8KB_PTR_REG 0x59 |
#define ASI_DMMU_TSB_64KB_PTR_REG 0x5a |
63,7 → 63,7 |
#define ASI_DTLB_TAG_READ_REG 0x5e |
#define ASI_DMMU_DEMAP 0x5f |
/** Virtual Addresses within ASI_DMMU. */ |
/* Virtual Addresses within ASI_DMMU. */ |
#define VA_DMMU_TAG_TARGET 0x0 /**< DMMU tag target register. */ |
#define VA_PRIMARY_CONTEXT_REG 0x8 /**< DMMU primary context register. */ |
#define VA_SECONDARY_CONTEXT_REG 0x10 /**< DMMU secondary context register. */ |
/trunk/kernel/arch/sparc64/include/drivers/z8530.h |
---|
70,6 → 70,9 |
#define RR14 14 |
#define RR15 15 |
/* Write Register 0 */ |
#define WR0_ERR_RST (0x6<<3) |
/* Write Register 1 */ |
#define WR1_RID (0x0<<3) /** Receive Interrupts Disabled. */ |
#define WR1_RIFCSC (0x1<<3) /** Receive Interrupt on First Character or Special Condition. */ |
/trunk/kernel/arch/sparc64/include/drivers/fhc.h |
---|
0,0 → 1,48 |
/* |
* Copyright (C) 2006 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup sparc64 |
* @{ |
*/ |
/** @file |
*/ |
#ifndef KERN_sparc64_FHC_H_ |
#define KERN_sparc64_FHC_H_ |
#include <arch/types.h> |
extern volatile uint32_t *fhc; |
extern void fhc_init(void); |
extern void fhc_uart_reset(void); |
#endif |
/** @} |
*/ |
/trunk/kernel/arch/sparc64/include/drivers/ns16550.h |
---|
39,6 → 39,7 |
#include <arch/drivers/kbd.h> |
#define RBR_REG 0 /** Receiver Buffer Register. */ |
#define IER_REG 1 /** Interrupt Enable Register. */ |
#define LSR_REG 5 /** Line Status Register. */ |
static inline uint8_t ns16550_rbr_read(void) |
46,6 → 47,16 |
return kbd_virt_address[RBR_REG]; |
} |
static inline uint8_t ns16550_ier_read(void) |
{ |
return kbd_virt_address[IER_REG]; |
} |
static inline void ns16550_ier_write(uint8_t v) |
{ |
kbd_virt_address[IER_REG] = v; |
} |
static inline uint8_t ns16550_lsr_read(void) |
{ |
return kbd_virt_address[LSR_REG]; |
/trunk/kernel/arch/sparc64/Makefile.inc |
---|
101,3 → 101,8 |
arch/$(ARCH)/src/ddi/ddi.c \ |
arch/$(ARCH)/src/drivers/tick.c \ |
arch/$(ARCH)/src/drivers/kbd.c |
ifdef CONFIG_Z8530 |
ARCH_SOURCES += \ |
arch/$(ARCH)/src/drivers/fhc.c |
endif |
/trunk/kernel/arch/sparc64/src/console.c |
---|
84,7 → 84,7 |
while (1) { |
#ifdef CONFIG_Z8530 |
z8530_poll(); |
return; |
#endif |
#ifdef CONFIG_NS16550 |
ns16550_poll(); |
/trunk/kernel/arch/sparc64/src/trap/interrupt.c |
---|
33,11 → 33,17 |
*/ |
#include <arch/interrupt.h> |
#include <arch/trap/interrupt.h> |
#include <interrupt.h> |
#include <arch/drivers/fhc.h> |
#include <arch/types.h> |
#include <debug.h> |
#include <ipc/sysipc.h> |
#include <arch/asm.h> |
#include <arch/barrier.h> |
#include <genarch/kbd/z8530.h> |
/** Register Interrupt Level Handler. |
* |
* @param n Interrupt Level (1 - 15). |
58,6 → 64,33 |
/* TODO */ |
} |
void interrupt(void) |
{ |
uint64_t intrcv; |
uint64_t data0; |
intrcv = asi_u64_read(ASI_INTR_RECEIVE, 0); |
data0 = asi_u64_read(ASI_UDB_INTR_R, ASI_UDB_INTR_R_DATA_0); |
switch (data0) { |
#ifdef CONFIG_Z8530 |
case Z8530_INTRCV_DATA0: |
/* |
* So far, we know we got this interrupt through the FHC. |
* Since we don't have enough information about the FHC and |
* because the interrupt looks like level sensitive, |
* we cannot handle it by scheduling one of the level |
* interrupt traps. Call the interrupt handler directly. |
*/ |
fhc_uart_reset(); |
z8530_interrupt(); |
break; |
#endif |
} |
membar(); |
asi_u64_write(ASI_INTR_RECEIVE, 0, 0); |
} |
/** @} |
*/ |
/trunk/kernel/arch/sparc64/src/drivers/kbd.c |
---|
60,7 → 60,7 |
* We need to pass aligned address to hw_map(). |
* However, the physical keyboard address can |
* be pretty much unaligned on some systems |
* (e.g. Ultra 5, Ultras 60). |
* (e.g. Ultra 5, Ultra 60). |
*/ |
aligned_addr = ALIGN_DOWN(bootinfo.keyboard.addr, PAGE_SIZE); |
offset = bootinfo.keyboard.addr - aligned_addr; |
/trunk/kernel/arch/sparc64/src/drivers/fhc.c |
---|
0,0 → 1,75 |
/* |
* Copyright (C) 2006 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup sparc64 |
* @{ |
*/ |
/** |
* @file |
* @brief FireHose Controller (FHC) driver. |
* |
* Note that this driver is a result of reverse engineering |
* rather than implementation of a specification. This |
* is due to the fact that the FHC documentation is not |
* publicly available. |
*/ |
#include <arch/drivers/fhc.h> |
#include <arch/mm/page.h> |
#include <arch/types.h> |
#include <typedefs.h> |
#include <genarch/kbd/z8530.h> |
volatile uint32_t *fhc = NULL; |
#define FHC_UART_ADDR 0x1fff8808000ULL /* hardcoded for Simics simulation */ |
#define FHC_UART_IMAP 0x0 |
#define FHC_UART_ICLR 0x4 |
void fhc_init(void) |
{ |
fhc = (void *) hw_map(FHC_UART_ADDR, PAGE_SIZE); |
(void) fhc[FHC_UART_ICLR]; |
fhc[FHC_UART_ICLR] = 0; |
(void) fhc[FHC_UART_IMAP]; |
fhc[FHC_UART_IMAP] = Z8530_INTRCV_DATA0; /* hardcoded for Simics simulation */ |
(void) fhc[FHC_UART_IMAP]; |
fhc[FHC_UART_IMAP] = 0x80000000; /* hardcoded for Simics simulation */ |
} |
void fhc_uart_reset(void) |
{ |
(void) fhc[FHC_UART_ICLR]; |
fhc[FHC_UART_ICLR] = 0; |
} |
/** @} |
*/ |
/trunk/kernel/arch/sparc64/src/drivers/tick.c |
---|
90,4 → 90,3 |
/** @} |
*/ |