Subversion Repositories HelenOS

Compare Revisions

Ignore whitespace Rev 1266 → Rev 1267

//kernel/trunk/arch/ppc32/include/asm/regname.h
194,6 → 194,8
/* MSR bits */
#define msr_ir (1 << 4)
#define msr_dr (1 << 5)
#define msr_pr (1 << 14)
#define msr_ee (1 << 15)
 
/* HID0 bits */
#define hid0_ice (1 << 15)
//kernel/trunk/arch/ppc32/include/interrupt.h
29,8 → 29,7
#ifndef __ppc32_INTERRUPT_H__
#define __ppc32_INTERRUPT_H__
 
#define IRQ_COUNT 1 /* TODO */
 
#define IRQ_COUNT 1
#define IVT_ITEMS 15
#define INT_OFFSET 0
 
//kernel/trunk/arch/ppc32/include/exception.h
47,7 → 47,6
__u32 r9;
__u32 r10;
__u32 r11;
__u32 r12;
__u32 r13;
__u32 r14;
__u32 r15;
//kernel/trunk/arch/ppc32/include/byteorder.h
51,8 → 51,12
{
__address v;
__asm__ volatile ("lwbrx %0, %1, %2\n" : "=r" (v) : "i" (0) , "r" (&n));
asm volatile (
"lwbrx %0, %1, %2\n"
: "=r" (v)
: "i" (0), "r" (&n)
);
return v;
}
 
#endif
//kernel/trunk/arch/ppc32/include/cpuid.h
38,8 → 38,8
 
static inline void cpu_version(struct cpu_info *info)
{
__asm__ volatile (
"mfspr %0, 287\n"
asm volatile (
"mfpvr %0\n"
: "=r" (*info)
);
}
//kernel/trunk/arch/ppc32/include/atomic.h
33,7 → 33,7
{
long tmp;
 
asm __volatile__ (
asm volatile (
"1:\n"
"lwarx %0, 0, %2\n"
"addic %0, %0, 1\n"
41,7 → 41,8
"bne- 1b"
: "=&r" (tmp), "=m" (val->count)
: "r" (&val->count), "m" (val->count)
: "cc");
: "cc"
);
}
 
static inline void atomic_dec(atomic_t *val)
48,7 → 49,7
{
long tmp;
 
asm __volatile__(
asm volatile (
"1:\n"
"lwarx %0, 0, %2\n"
"addic %0, %0, -1\n"
56,7 → 57,8
"bne- 1b"
: "=&r" (tmp), "=m" (val->count)
: "r" (&val->count), "m" (val->count)
: "cc");
: "cc"
);
}
 
static inline long atomic_postinc(atomic_t *val)
//kernel/trunk/arch/ppc32/include/asm.h
40,10 → 40,10
* @return Old interrupt priority level.
*/
static inline ipl_t interrupts_enable(void) {
ipl_t v;
ipl_t v = 0;
ipl_t tmp;
__asm__ volatile (
asm volatile (
"mfmsr %0\n"
"mfmsr %1\n"
"ori %1, %1, 1 << 15\n"
64,7 → 64,7
ipl_t v;
ipl_t tmp;
__asm__ volatile (
asm volatile (
"mfmsr %0\n"
"mfmsr %1\n"
"rlwinm %1, %1, 0, 17, 15\n"
83,7 → 83,7
static inline void interrupts_restore(ipl_t ipl) {
ipl_t tmp;
__asm__ volatile (
asm volatile (
"mfmsr %1\n"
"rlwimi %0, %1, 0, 17, 15\n"
"cmpw 0, %0, %1\n"
103,7 → 103,8
*/
static inline ipl_t interrupts_read(void) {
ipl_t v;
__asm__ volatile (
asm volatile (
"mfmsr %0\n"
: "=r" (v)
);
120,8 → 121,11
{
__address v;
__asm__ volatile ("and %0, %%sp, %1\n" : "=r" (v) : "r" (~(STACK_SIZE-1)));
asm volatile (
"and %0, %%sp, %1\n"
: "=r" (v)
: "r" (~(STACK_SIZE - 1))
);
return v;
}
 
//kernel/trunk/arch/ppc32/include/barrier.h
29,11 → 29,11
#ifndef __ppc32_BARRIER_H__
#define __ppc32_BARRIER_H__
 
#define CS_ENTER_BARRIER() __asm__ volatile ("" ::: "memory")
#define CS_LEAVE_BARRIER() __asm__ volatile ("" ::: "memory")
#define CS_ENTER_BARRIER() asm volatile ("" ::: "memory")
#define CS_LEAVE_BARRIER() asm volatile ("" ::: "memory")
 
#define memory_barrier() __asm__ volatile ("sync" ::: "memory")
#define read_barrier() __asm__ volatile ("sync" ::: "memory")
#define write_barrier() __asm__ volatile ("eieio" ::: "memory")
#define memory_barrier() asm volatile ("sync" ::: "memory")
#define read_barrier() asm volatile ("sync" ::: "memory")
#define write_barrier() asm volatile ("eieio" ::: "memory")
 
#endif