//SPARTAN/trunk/arch/mips/src/mips.c |
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37,12 → 37,12 |
* Clear the error level. |
*/ |
cp0_status_write(cp0_status_read() & ~(cp0_status_bev_bootstrap_bit|cp0_status_erl_error_bit)); |
/* |
* Unmask hardware clock interrupt. |
*/ |
cp0_status_write(cp0_status_read() | (1<<cp0_status_im7_shift)); |
/* |
* Start hardware clock. |
*/ |