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1301 jermar 1
/*
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 *  The PCI Library -- Direct Configuration access via i386 Ports
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 *
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 *  Copyright (c) 1997--2004 Martin Mares <mj@ucw.cz>
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 *
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 *  Modified and ported to HelenOS by Jakub Jermar.
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 *
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 *  Can be freely distributed and used under the terms of the GNU GPL.
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 */
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#include <unistd.h>
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#include "internal.h"
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static inline void outb(u8 b, u16 port)
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{
1302 jermar 17
    asm volatile ("outb %0, %1\n" :: "a" (b), "d" (port));
1301 jermar 18
}
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static inline void outw(u16 w, u16 port)
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{
1302 jermar 22
    asm volatile ("outw %0, %1\n" :: "a" (w), "d" (port));
1301 jermar 23
}
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25
static inline void outl(u32 l, u16 port)
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{
1302 jermar 27
    asm volatile ("outl %0, %1\n" :: "a" (l), "d" (port));
1301 jermar 28
}
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30
static inline u8 inb(u16 port)
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{
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    u8 val;
1302 jermar 33
 
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    asm volatile ("inb %1, %0 \n" : "=a" (val) : "d"(port));
1301 jermar 35
    return val;
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}
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static inline u16 inw(u16 port)
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{
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    u16 val;
1302 jermar 41
 
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    asm volatile ("inw %1, %0 \n" : "=a" (val) : "d"(port));
1301 jermar 43
    return val;
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}
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static inline u32 inl(u16 port)
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{
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    u32 val;
1302 jermar 49
 
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    asm volatile ("inl %1, %0 \n" : "=a" (val) : "d"(port));
1301 jermar 51
    return val;
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}
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1302 jermar 54
static void conf12_init(struct pci_access *a)
1301 jermar 55
{
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}
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1302 jermar 58
static void conf12_cleanup(struct pci_access *a UNUSED)
1301 jermar 59
{
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}
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/*
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 * Before we decide to use direct hardware access mechanisms, we try to do some
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 * trivial checks to ensure it at least _seems_ to be working -- we just test
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 * whether bus 00 contains a host bridge (this is similar to checking
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 * techniques used in XFree86, but ours should be more reliable since we
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 * attempt to make use of direct access hints provided by the PCI BIOS).
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 *
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 * This should be close to trivial, but it isn't, because there are buggy
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 * chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID.
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 */
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1302 jermar 73
static int intel_sanity_check(struct pci_access *a, struct pci_methods *m)
1301 jermar 74
{
1302 jermar 75
    struct pci_dev d;
1301 jermar 76
 
1302 jermar 77
    a->debug("...sanity check");
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    d.bus = 0;
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    d.func = 0;
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    for (d.dev = 0; d.dev < 32; d.dev++) {
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        u16 class, vendor;
1307 jermar 82
        if (m->read(&d, PCI_CLASS_DEVICE, (byte *) & class,
1302 jermar 83
             sizeof(class))
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            && (class == cpu_to_le16(PCI_CLASS_BRIDGE_HOST)
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            || class == cpu_to_le16(PCI_CLASS_DISPLAY_VGA))
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            || m->read(&d, PCI_VENDOR_ID, (byte *) & vendor,
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                   sizeof(vendor))
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            && (vendor == cpu_to_le16(PCI_VENDOR_ID_INTEL)
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            || vendor == cpu_to_le16(PCI_VENDOR_ID_COMPAQ))) {
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            a->debug("...outside the Asylum at 0/%02x/0",
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                 d.dev);
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            return 1;
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        }
1301 jermar 94
    }
1302 jermar 95
    a->debug("...insane");
96
    return 0;
1301 jermar 97
}
98
 
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/*
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 *  Configuration type 1
101
 */
102
 
103
#define CONFIG_CMD(bus, device_fn, where)   (0x80000000 | (bus << 16) | (device_fn << 8) | (where & ~3))
104
 
1302 jermar 105
static int conf1_detect(struct pci_access *a)
1301 jermar 106
{
1302 jermar 107
    unsigned int tmp;
108
    int res = 0;
1301 jermar 109
 
1302 jermar 110
    outb(0x01, 0xCFB);
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    tmp = inl(0xCF8);
112
    outl(0x80000000, 0xCF8);
113
    if (inl(0xCF8) == 0x80000000)
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        res = 1;
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    outl(tmp, 0xCF8);
116
    if (res)
117
        res = intel_sanity_check(a, &pm_intel_conf1);
118
    return res;
1301 jermar 119
}
120
 
1302 jermar 121
static int conf1_read(struct pci_dev *d, int pos, byte * buf, int len)
1301 jermar 122
{
1302 jermar 123
    int addr = 0xcfc + (pos & 3);
1301 jermar 124
 
1302 jermar 125
    if (pos >= 256)
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        return 0;
1301 jermar 127
 
1302 jermar 128
    outl(0x80000000 | ((d->bus & 0xff) << 16) |
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         (PCI_DEVFN(d->dev, d->func) << 8) | (pos & ~3), 0xcf8);
1301 jermar 130
 
1302 jermar 131
    switch (len) {
132
    case 1:
133
        buf[0] = inb(addr);
134
        break;
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    case 2:
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        ((u16 *) buf)[0] = cpu_to_le16(inw(addr));
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        break;
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    case 4:
139
        ((u32 *) buf)[0] = cpu_to_le32(inl(addr));
140
        break;
141
    default:
142
        return pci_generic_block_read(d, pos, buf, len);
143
    }
144
    return 1;
1301 jermar 145
}
146
 
1302 jermar 147
static int conf1_write(struct pci_dev *d, int pos, byte * buf, int len)
1301 jermar 148
{
1302 jermar 149
    int addr = 0xcfc + (pos & 3);
1301 jermar 150
 
1302 jermar 151
    if (pos >= 256)
152
        return 0;
1301 jermar 153
 
1302 jermar 154
    outl(0x80000000 | ((d->bus & 0xff) << 16) |
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         (PCI_DEVFN(d->dev, d->func) << 8) | (pos & ~3), 0xcf8);
1301 jermar 156
 
1302 jermar 157
    switch (len) {
158
    case 1:
159
        outb(buf[0], addr);
160
        break;
161
    case 2:
162
        outw(le16_to_cpu(((u16 *) buf)[0]), addr);
163
        break;
164
    case 4:
165
        outl(le32_to_cpu(((u32 *) buf)[0]), addr);
166
        break;
167
    default:
168
        return pci_generic_block_write(d, pos, buf, len);
169
    }
170
    return 1;
1301 jermar 171
}
172
 
173
/*
174
 *  Configuration type 2. Obsolete and brain-damaged, but existing.
175
 */
176
 
1302 jermar 177
static int conf2_detect(struct pci_access *a)
1301 jermar 178
{
1302 jermar 179
    /* This is ugly and tends to produce false positives. Beware. */
180
    outb(0x00, 0xCFB);
181
    outb(0x00, 0xCF8);
182
    outb(0x00, 0xCFA);
183
    if (inb(0xCF8) == 0x00 && inb(0xCFA) == 0x00)
184
        return intel_sanity_check(a, &pm_intel_conf2);
185
    else
186
        return 0;
1301 jermar 187
}
188
 
1302 jermar 189
static int conf2_read(struct pci_dev *d, int pos, byte * buf, int len)
1301 jermar 190
{
1302 jermar 191
    int addr = 0xc000 | (d->dev << 8) | pos;
1301 jermar 192
 
1302 jermar 193
    if (pos >= 256)
194
        return 0;
1301 jermar 195
 
1302 jermar 196
    if (d->dev >= 16)
197
        /* conf2 supports only 16 devices per bus */
198
        return 0;
199
    outb((d->func << 1) | 0xf0, 0xcf8);
200
    outb(d->bus, 0xcfa);
201
    switch (len) {
202
    case 1:
203
        buf[0] = inb(addr);
204
        break;
205
    case 2:
206
        ((u16 *) buf)[0] = cpu_to_le16(inw(addr));
207
        break;
208
    case 4:
209
        ((u32 *) buf)[0] = cpu_to_le32(inl(addr));
210
        break;
211
    default:
212
        outb(0, 0xcf8);
213
        return pci_generic_block_read(d, pos, buf, len);
214
    }
215
    outb(0, 0xcf8);
216
    return 1;
1301 jermar 217
}
218
 
1302 jermar 219
static int conf2_write(struct pci_dev *d, int pos, byte * buf, int len)
1301 jermar 220
{
1302 jermar 221
    int addr = 0xc000 | (d->dev << 8) | pos;
1301 jermar 222
 
1302 jermar 223
    if (pos >= 256)
224
        return 0;
1301 jermar 225
 
1302 jermar 226
    if (d->dev >= 16)
1307 jermar 227
        d->access->error("conf2_write: only first 16 devices exist.");
1302 jermar 228
    outb((d->func << 1) | 0xf0, 0xcf8);
229
    outb(d->bus, 0xcfa);
230
    switch (len) {
231
    case 1:
232
        outb(buf[0], addr);
233
        break;
234
    case 2:
235
        outw(le16_to_cpu(*(u16 *) buf), addr);
236
        break;
237
    case 4:
238
        outl(le32_to_cpu(*(u32 *) buf), addr);
239
        break;
240
    default:
241
        outb(0, 0xcf8);
242
        return pci_generic_block_write(d, pos, buf, len);
243
    }
244
    outb(0, 0xcf8);
245
    return 1;
1301 jermar 246
}
247
 
248
struct pci_methods pm_intel_conf1 = {
1302 jermar 249
    "Intel-conf1",
250
    NULL,           /* config */
251
    conf1_detect,
252
    conf12_init,
253
    conf12_cleanup,
254
    pci_generic_scan,
255
    pci_generic_fill_info,
256
    conf1_read,
257
    conf1_write,
258
    NULL,           /* init_dev */
259
    NULL            /* cleanup_dev */
1301 jermar 260
};
261
 
262
struct pci_methods pm_intel_conf2 = {
1302 jermar 263
    "Intel-conf2",
264
    NULL,           /* config */
265
    conf2_detect,
266
    conf12_init,
267
    conf12_cleanup,
268
    pci_generic_scan,
269
    pci_generic_fill_info,
270
    conf2_read,
271
    conf2_write,
272
    NULL,           /* init_dev */
273
    NULL            /* cleanup_dev */
1301 jermar 274
};