Rev 150 | Go to most recent revision | Details | Compare with Previous | Last modification | View Log | RSS feed
| Rev | Author | Line No. | Line |
|---|---|---|---|
| 154 | jermar | 1 | + implement true memory barriers for all architectures |
| 2 | |||
| 1 | jermar | 3 | + implement true memory management |
| 154 | jermar | 4 | + [ia32] use int 0x15 ax=0xe820 to get memory map and memory size [DONE] |
| 1 | jermar | 5 | + [mips] use some heuristics to get memory map and memory size |
| 154 | jermar | 6 | + reimplement heap so that it can allocate/deallocate |
| 7 | itself frames as necessary |
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| 8 | + provide native four-level portable page table interface [DONE] |
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| 1 | jermar | 9 | + every architecture uses its native page table format |
| 154 | jermar | 10 | + kernel provides unified four-level page table interface |
| 11 | for all architectures |
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| 12 | + track usage of frames containing middle-level page tables |
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| 13 | (frame leak) |
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| 1 | jermar | 14 | |
| 15 | + get user mode support for all architectures |
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| 16 | |||
| 17 | + save/restore floating point context on context switch |
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| 154 | jermar | 18 | + [ia32] lazy context switch using TS flag [DONE] |
| 73 | vana | 19 | + [ia32] MMX,SSE1-.. initialization |
| 154 | jermar | 20 | + [ia32] review privilege separation [DONE] |
| 21 | + zero IOPL in EFLAGS [DONE] |
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| 22 | + before IRET (from SYSCALL), zero NT in EFLAGS [DONE] |
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| 1 | jermar | 23 | + [ia32] review the cache controling bits in CR0 register |
| 154 | jermar | 24 | + [ia32] zero the alignment exception bit in EFLAGS [DONE] |
| 25 | - Task changed to clear AM in CR0 so that |
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| 26 | the alignment check is disabled globally |
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| 1 | jermar | 27 | + make emulated architectures also work on real hardware |
| 28 | + bring in support for other architectures (e.g. PowerPC) |