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570 jermar 1
/*
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 * Copyright (C) 2005 Jakub Jermar
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 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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1702 cejka 29
 /** @addtogroup sparc64mm 
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 * @{
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 */
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/** @file
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 */
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570 jermar 35
#include <arch/mm/tlb.h>
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#include <mm/tlb.h>
619 jermar 37
#include <arch/mm/frame.h>
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#include <arch/mm/page.h>
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#include <arch/mm/mmu.h>
877 jermar 40
#include <mm/asid.h>
570 jermar 41
#include <print.h>
617 jermar 42
#include <arch/types.h>
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#include <typedefs.h>
619 jermar 44
#include <config.h>
630 jermar 45
#include <arch/trap/trap.h>
863 jermar 46
#include <panic.h>
873 jermar 47
#include <arch/asm.h>
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#include <symtab.h>
894 jermar 49
 
883 jermar 50
#include <arch/drivers/fb.h>
895 jermar 51
#include <arch/drivers/i8042.h>
570 jermar 52
 
873 jermar 53
char *context_encoding[] = {
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    "Primary",
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    "Secondary",
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    "Nucleus",
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    "Reserved"
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};
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619 jermar 60
/** Initialize ITLB and DTLB.
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 *
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 * The goal of this function is to disable MMU
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 * so that both TLBs can be purged and new
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 * kernel 4M locked entry can be installed.
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 * After TLB is initialized, MMU is enabled
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 * again.
627 jermar 67
 *
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 * Switching MMU off imposes the requirement for
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 * the kernel to run in identity mapped environment.
619 jermar 70
 */
570 jermar 71
void tlb_arch_init(void)
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{
619 jermar 73
    tlb_tag_access_reg_t tag;
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    tlb_data_t data;
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    frame_address_t fr;
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    page_address_t pg;
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    fr.address = config.base;
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    pg.address = config.base;
646 jermar 80
 
619 jermar 81
    immu_disable();
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    dmmu_disable();
898 jermar 83
 
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    /*
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     * Demap everything, especially OpenFirmware.
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     */
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    itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
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    dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
619 jermar 89
 
90
    /*
846 jermar 91
     * We do identity mapping of 4M-page at 4M.
619 jermar 92
     */
877 jermar 93
    tag.value = ASID_KERNEL;
619 jermar 94
    tag.vpn = pg.vpn;
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    itlb_tag_access_write(tag.value);
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    dtlb_tag_access_write(tag.value);
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    data.value = 0;
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    data.v = true;
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    data.size = PAGESIZE_4M;
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    data.pfn = fr.pfn;
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    data.l = true;
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    data.cp = 1;
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    data.cv = 1;
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    data.p = true;
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    data.w = true;
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    data.g = true;
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110
    itlb_data_in_write(data.value);
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    dtlb_data_in_write(data.value);
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627 jermar 113
    /*
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     * Register window traps can occur before MMU is enabled again.
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     * This ensures that any such traps will be handled from
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     * kernel identity mapped trap handler.
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     */
118
    trap_switch_trap_table();
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619 jermar 120
    tlb_invalidate_all();
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122
    dmmu_enable();
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    immu_enable();
897 jermar 124
}
873 jermar 125
 
897 jermar 126
/** Insert privileged mapping into DMMU TLB.
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 *
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 * @param page Virtual page address.
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 * @param frame Physical frame address.
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 * @param pagesize Page size.
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 * @param locked True for permanent mappings, false otherwise.
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 * @param cacheable True if the mapping is cacheable, false otherwise.
133
 */
134
void dtlb_insert_mapping(__address page, __address frame, int pagesize, bool locked, bool cacheable)
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{
136
    tlb_tag_access_reg_t tag;
137
    tlb_data_t data;
138
    page_address_t pg;
139
    frame_address_t fr;
873 jermar 140
 
897 jermar 141
    pg.address = page;
142
    fr.address = frame;
873 jermar 143
 
894 jermar 144
    tag.value = ASID_KERNEL;
145
    tag.vpn = pg.vpn;
146
 
147
    dtlb_tag_access_write(tag.value);
148
 
149
    data.value = 0;
150
    data.v = true;
897 jermar 151
    data.size = pagesize;
894 jermar 152
    data.pfn = fr.pfn;
897 jermar 153
    data.l = locked;
154
    data.cp = cacheable;
155
    data.cv = cacheable;
894 jermar 156
    data.p = true;
157
    data.w = true;
158
    data.g = true;
159
 
160
    dtlb_data_in_write(data.value);
570 jermar 161
}
162
 
863 jermar 163
/** ITLB miss handler. */
164
void fast_instruction_access_mmu_miss(void)
165
{
166
    panic("%s\n", __FUNCTION__);
167
}
168
 
169
/** DTLB miss handler. */
170
void fast_data_access_mmu_miss(void)
171
{
877 jermar 172
    tlb_tag_access_reg_t tag;
173
    __address tpc;
873 jermar 174
    char *tpc_str;
883 jermar 175
 
877 jermar 176
    tag.value = dtlb_tag_access_read();
177
    if (tag.context != ASID_KERNEL || tag.vpn == 0) {
178
        tpc = tpc_read();
179
        tpc_str = get_symtab_entry(tpc);
873 jermar 180
 
1221 decky 181
        printf("Faulting page: %p, ASID=%d\n", tag.vpn * PAGE_SIZE, tag.context);
182
        printf("TPC=%p, (%s)\n", tpc, tpc_str ? tpc_str : "?");
877 jermar 183
        panic("%s\n", __FUNCTION__);
184
    }
185
 
186
    /*
187
     * Identity map piece of faulting kernel address space.
188
     */
897 jermar 189
    dtlb_insert_mapping(tag.vpn * PAGE_SIZE, tag.vpn * FRAME_SIZE, PAGESIZE_8K, false, true);
863 jermar 190
}
191
 
192
/** DTLB protection fault handler. */
193
void fast_data_access_protection(void)
194
{
195
    panic("%s\n", __FUNCTION__);
196
}
197
 
570 jermar 198
/** Print contents of both TLBs. */
199
void tlb_print(void)
200
{
201
    int i;
202
    tlb_data_t d;
203
    tlb_tag_read_reg_t t;
204
 
205
    printf("I-TLB contents:\n");
206
    for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
207
        d.value = itlb_data_access_read(i);
613 jermar 208
        t.value = itlb_tag_read_read(i);
570 jermar 209
 
1735 decky 210
        printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
617 jermar 211
            i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
570 jermar 212
    }
213
 
214
    printf("D-TLB contents:\n");
215
    for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
216
        d.value = dtlb_data_access_read(i);
613 jermar 217
        t.value = dtlb_tag_read_read(i);
570 jermar 218
 
1735 decky 219
        printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
617 jermar 220
            i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
570 jermar 221
    }
222
 
223
}
617 jermar 224
 
225
/** Invalidate all unlocked ITLB and DTLB entries. */
226
void tlb_invalidate_all(void)
227
{
228
    int i;
229
    tlb_data_t d;
230
    tlb_tag_read_reg_t t;
231
 
232
    for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
233
        d.value = itlb_data_access_read(i);
234
        if (!d.l) {
235
            t.value = itlb_tag_read_read(i);
236
            d.v = false;
237
            itlb_tag_access_write(t.value);
238
            itlb_data_access_write(i, d.value);
239
        }
240
    }
241
 
242
    for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
243
        d.value = dtlb_data_access_read(i);
244
        if (!d.l) {
245
            t.value = dtlb_tag_read_read(i);
246
            d.v = false;
247
            dtlb_tag_access_write(t.value);
248
            dtlb_data_access_write(i, d.value);
249
        }
250
    }
251
 
252
}
253
 
254
/** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context).
255
 *
256
 * @param asid Address Space ID.
257
 */
258
void tlb_invalidate_asid(asid_t asid)
259
{
260
    /* TODO: write asid to some Context register and encode the register in second parameter below. */
261
    itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
262
    dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
263
}
264
 
727 jermar 265
/** Invalidate all ITLB and DTLB entries for specified page range in specified address space.
617 jermar 266
 *
267
 * @param asid Address Space ID.
727 jermar 268
 * @param page First page which to sweep out from ITLB and DTLB.
269
 * @param cnt Number of ITLB and DTLB entries to invalidate.
617 jermar 270
 */
727 jermar 271
void tlb_invalidate_pages(asid_t asid, __address page, count_t cnt)
617 jermar 272
{
727 jermar 273
    int i;
274
 
275
    for (i = 0; i < cnt; i++) {
276
        /* TODO: write asid to some Context register and encode the register in second parameter below. */
277
        itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);
278
        dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);
279
    }
617 jermar 280
}
1702 cejka 281
 
282
 /** @}
283
 */
284