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| 418 | jermar | 1 | /* |
| 2 | * Copyright (C) 2005 Jakub Jermar |
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| 3 | * All rights reserved. |
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| 4 | * |
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| 5 | * Redistribution and use in source and binary forms, with or without |
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| 6 | * modification, are permitted provided that the following conditions |
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| 7 | * are met: |
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| 8 | * |
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| 9 | * - Redistributions of source code must retain the above copyright |
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| 10 | * notice, this list of conditions and the following disclaimer. |
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| 11 | * - Redistributions in binary form must reproduce the above copyright |
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| 12 | * notice, this list of conditions and the following disclaimer in the |
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| 13 | * documentation and/or other materials provided with the distribution. |
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| 14 | * - The name of the author may not be used to endorse or promote products |
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| 15 | * derived from this software without specific prior written permission. |
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| 16 | * |
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 27 | */ |
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| 28 | |||
| 29 | #ifndef __sparc64_TLB_H__ |
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| 30 | #define __sparc64_TLB_H__ |
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| 31 | |||
| 530 | jermar | 32 | #include <arch/mm/tte.h> |
| 619 | jermar | 33 | #include <arch/mm/mmu.h> |
| 617 | jermar | 34 | #include <arch/mm/page.h> |
| 569 | jermar | 35 | #include <arch/asm.h> |
| 613 | jermar | 36 | #include <arch/barrier.h> |
| 569 | jermar | 37 | #include <arch/types.h> |
| 38 | #include <typedefs.h> |
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| 530 | jermar | 39 | |
| 569 | jermar | 40 | #define ITLB_ENTRY_COUNT 64 |
| 41 | #define DTLB_ENTRY_COUNT 64 |
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| 42 | |||
| 619 | jermar | 43 | /** Page sizes. */ |
| 44 | #define PAGESIZE_8K 0 |
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| 45 | #define PAGESIZE_64K 1 |
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| 46 | #define PAGESIZE_512K 2 |
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| 47 | #define PAGESIZE_4M 3 |
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| 531 | jermar | 48 | |
| 873 | jermar | 49 | union tlb_context_reg { |
| 50 | __u64 v; |
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| 51 | struct { |
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| 52 | unsigned long : 51; |
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| 53 | unsigned context : 13; /**< Context/ASID. */ |
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| 54 | } __attribute__ ((packed)); |
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| 55 | }; |
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| 56 | typedef union tlb_context_reg tlb_context_reg_t; |
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| 57 | |||
| 530 | jermar | 58 | /** I-/D-TLB Data In/Access Register type. */ |
| 59 | typedef tte_data_t tlb_data_t; |
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| 60 | |||
| 569 | jermar | 61 | /** I-/D-TLB Data Access Address in Alternate Space. */ |
| 62 | union tlb_data_access_addr { |
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| 63 | __u64 value; |
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| 64 | struct { |
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| 65 | __u64 : 55; |
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| 66 | unsigned tlb_entry : 6; |
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| 67 | unsigned : 3; |
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| 68 | } __attribute__ ((packed)); |
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| 69 | }; |
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| 70 | typedef union tlb_data_access_addr tlb_data_access_addr_t; |
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| 71 | typedef union tlb_data_access_addr tlb_tag_read_addr_t; |
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| 418 | jermar | 72 | |
| 569 | jermar | 73 | /** I-/D-TLB Tag Read Register. */ |
| 74 | union tlb_tag_read_reg { |
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| 75 | __u64 value; |
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| 76 | struct { |
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| 617 | jermar | 77 | __u64 vpn : 51; /**< Virtual Address bits 63:13. */ |
| 569 | jermar | 78 | unsigned context : 13; /**< Context identifier. */ |
| 79 | } __attribute__ ((packed)); |
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| 80 | }; |
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| 81 | typedef union tlb_tag_read_reg tlb_tag_read_reg_t; |
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| 613 | jermar | 82 | typedef union tlb_tag_read_reg tlb_tag_access_reg_t; |
| 569 | jermar | 83 | |
| 617 | jermar | 84 | /** TLB Demap Operation types. */ |
| 85 | #define TLB_DEMAP_PAGE 0 |
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| 86 | #define TLB_DEMAP_CONTEXT 1 |
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| 87 | |||
| 88 | /** TLB Demap Operation Context register encodings. */ |
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| 89 | #define TLB_DEMAP_PRIMARY 0 |
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| 90 | #define TLB_DEMAP_SECONDARY 1 |
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| 91 | #define TLB_DEMAP_NUCLEUS 2 |
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| 92 | |||
| 93 | /** TLB Demap Operation Address. */ |
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| 94 | union tlb_demap_addr { |
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| 95 | __u64 value; |
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| 96 | struct { |
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| 97 | __u64 vpn: 51; /**< Virtual Address bits 63:13. */ |
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| 98 | unsigned : 6; /**< Ignored. */ |
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| 99 | unsigned type : 1; /**< The type of demap operation. */ |
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| 100 | unsigned context : 2; /**< Context register selection. */ |
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| 101 | unsigned : 4; /**< Zero. */ |
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| 102 | } __attribute__ ((packed)); |
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| 103 | }; |
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| 104 | typedef union tlb_demap_addr tlb_demap_addr_t; |
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| 105 | |||
| 873 | jermar | 106 | /** TLB Synchronous Fault Status Register. */ |
| 107 | union tlb_sfsr_reg { |
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| 108 | __u64 value; |
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| 109 | struct { |
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| 110 | unsigned long : 39; /**< Implementation dependent. */ |
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| 111 | unsigned nf : 1; /**< Nonfaulting load. */ |
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| 112 | unsigned asi : 8; /**< ASI. */ |
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| 113 | unsigned tm : 1; /**< TLB miss. */ |
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| 114 | unsigned : 3; |
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| 115 | unsigned ft : 5; /**< Fault type. */ |
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| 116 | unsigned e : 1; /**< Side-effect bit. */ |
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| 117 | unsigned ct : 2; /**< Context Register selection. */ |
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| 118 | unsigned pr : 1; /**< Privilege bit. */ |
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| 119 | unsigned w : 1; /**< Write bit. */ |
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| 120 | unsigned ow : 1; /**< Overwrite bit. */ |
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| 121 | unsigned fv : 1; /**< Fayult Valid bit. */ |
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| 122 | } __attribute__ ((packed)); |
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| 123 | }; |
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| 124 | typedef union tlb_sfsr_reg tlb_sfsr_reg_t; |
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| 125 | |||
| 126 | /** Read MMU Primary Context Register. |
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| 127 | * |
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| 128 | * @return Current value of Primary Context Register. |
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| 129 | */ |
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| 130 | static inline __u64 mmu_primary_context_read(void) |
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| 131 | { |
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| 132 | return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG); |
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| 133 | } |
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| 134 | |||
| 135 | /** Write MMU Primary Context Register. |
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| 136 | * |
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| 137 | * @param v New value of Primary Context Register. |
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| 138 | */ |
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| 139 | static inline void mmu_primary_context_write(__u64 v) |
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| 140 | { |
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| 141 | asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v); |
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| 142 | flush(); |
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| 143 | } |
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| 144 | |||
| 145 | /** Read MMU Secondary Context Register. |
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| 146 | * |
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| 147 | * @return Current value of Secondary Context Register. |
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| 148 | */ |
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| 149 | static inline __u64 mmu_secondary_context_read(void) |
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| 150 | { |
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| 151 | return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG); |
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| 152 | } |
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| 153 | |||
| 154 | /** Write MMU Primary Context Register. |
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| 155 | * |
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| 156 | * @param v New value of Primary Context Register. |
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| 157 | */ |
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| 158 | static inline void mmu_secondary_context_write(__u64 v) |
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| 159 | { |
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| 160 | asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v); |
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| 161 | flush(); |
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| 162 | } |
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| 163 | |||
| 569 | jermar | 164 | /** Read IMMU TLB Data Access Register. |
| 165 | * |
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| 166 | * @param entry TLB Entry index. |
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| 167 | * |
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| 168 | * @return Current value of specified IMMU TLB Data Access Register. |
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| 169 | */ |
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| 170 | static inline __u64 itlb_data_access_read(index_t entry) |
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| 171 | { |
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| 172 | tlb_data_access_addr_t reg; |
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| 173 | |||
| 174 | reg.value = 0; |
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| 175 | reg.tlb_entry = entry; |
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| 176 | return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value); |
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| 177 | } |
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| 178 | |||
| 617 | jermar | 179 | /** Write IMMU TLB Data Access Register. |
| 180 | * |
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| 181 | * @param entry TLB Entry index. |
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| 182 | * @param value Value to be written. |
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| 183 | */ |
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| 658 | jermar | 184 | static inline void itlb_data_access_write(index_t entry, __u64 value) |
| 617 | jermar | 185 | { |
| 186 | tlb_data_access_addr_t reg; |
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| 187 | |||
| 188 | reg.value = 0; |
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| 189 | reg.tlb_entry = entry; |
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| 190 | asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value); |
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| 191 | flush(); |
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| 192 | } |
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| 193 | |||
| 569 | jermar | 194 | /** Read DMMU TLB Data Access Register. |
| 195 | * |
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| 196 | * @param entry TLB Entry index. |
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| 197 | * |
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| 198 | * @return Current value of specified DMMU TLB Data Access Register. |
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| 199 | */ |
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| 200 | static inline __u64 dtlb_data_access_read(index_t entry) |
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| 201 | { |
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| 202 | tlb_data_access_addr_t reg; |
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| 203 | |||
| 204 | reg.value = 0; |
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| 205 | reg.tlb_entry = entry; |
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| 206 | return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value); |
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| 207 | } |
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| 208 | |||
| 617 | jermar | 209 | /** Write DMMU TLB Data Access Register. |
| 210 | * |
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| 211 | * @param entry TLB Entry index. |
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| 212 | * @param value Value to be written. |
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| 213 | */ |
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| 658 | jermar | 214 | static inline void dtlb_data_access_write(index_t entry, __u64 value) |
| 617 | jermar | 215 | { |
| 216 | tlb_data_access_addr_t reg; |
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| 217 | |||
| 218 | reg.value = 0; |
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| 219 | reg.tlb_entry = entry; |
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| 220 | asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value); |
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| 221 | flush(); |
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| 222 | } |
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| 223 | |||
| 569 | jermar | 224 | /** Read IMMU TLB Tag Read Register. |
| 225 | * |
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| 226 | * @param entry TLB Entry index. |
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| 227 | * |
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| 228 | * @return Current value of specified IMMU TLB Tag Read Register. |
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| 229 | */ |
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| 613 | jermar | 230 | static inline __u64 itlb_tag_read_read(index_t entry) |
| 569 | jermar | 231 | { |
| 232 | tlb_tag_read_addr_t tag; |
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| 233 | |||
| 234 | tag.value = 0; |
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| 235 | tag.tlb_entry = entry; |
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| 236 | return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value); |
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| 237 | } |
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| 238 | |||
| 239 | /** Read DMMU TLB Tag Read Register. |
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| 240 | * |
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| 241 | * @param entry TLB Entry index. |
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| 242 | * |
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| 243 | * @return Current value of specified DMMU TLB Tag Read Register. |
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| 244 | */ |
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| 613 | jermar | 245 | static inline __u64 dtlb_tag_read_read(index_t entry) |
| 569 | jermar | 246 | { |
| 247 | tlb_tag_read_addr_t tag; |
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| 248 | |||
| 249 | tag.value = 0; |
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| 250 | tag.tlb_entry = entry; |
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| 251 | return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value); |
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| 252 | } |
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| 253 | |||
| 613 | jermar | 254 | /** Write IMMU TLB Tag Access Register. |
| 255 | * |
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| 256 | * @param v Value to be written. |
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| 257 | */ |
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| 258 | static inline void itlb_tag_access_write(__u64 v) |
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| 259 | { |
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| 260 | asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v); |
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| 261 | flush(); |
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| 262 | } |
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| 263 | |||
| 264 | /** Write DMMU TLB Tag Access Register. |
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| 265 | * |
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| 266 | * @param v Value to be written. |
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| 267 | */ |
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| 268 | static inline void dtlb_tag_access_write(__u64 v) |
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| 269 | { |
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| 270 | asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v); |
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| 271 | flush(); |
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| 272 | } |
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| 273 | |||
| 274 | /** Write IMMU TLB Data in Register. |
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| 275 | * |
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| 276 | * @param v Value to be written. |
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| 277 | */ |
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| 278 | static inline void itlb_data_in_write(__u64 v) |
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| 279 | { |
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| 280 | asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v); |
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| 281 | flush(); |
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| 282 | } |
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| 283 | |||
| 284 | /** Write DMMU TLB Data in Register. |
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| 285 | * |
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| 286 | * @param v Value to be written. |
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| 287 | */ |
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| 288 | static inline void dtlb_data_in_write(__u64 v) |
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| 289 | { |
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| 290 | asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v); |
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| 291 | flush(); |
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| 292 | } |
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| 293 | |||
| 873 | jermar | 294 | /** Read ITLB Synchronous Fault Status Register. |
| 295 | * |
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| 296 | * @return Current content of I-SFSR register. |
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| 297 | */ |
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| 298 | static inline __u64 itlb_sfsr_read(void) |
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| 299 | { |
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| 300 | return asi_u64_read(ASI_IMMU, VA_IMMU_SFSR); |
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| 301 | } |
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| 302 | |||
| 303 | /** Write ITLB Synchronous Fault Status Register. |
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| 304 | * |
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| 305 | * @param v New value of I-SFSR register. |
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| 306 | */ |
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| 307 | static inline void itlb_sfsr_write(__u64 v) |
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| 308 | { |
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| 309 | asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v); |
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| 310 | flush(); |
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| 311 | } |
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| 312 | |||
| 313 | /** Read DTLB Synchronous Fault Status Register. |
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| 314 | * |
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| 315 | * @return Current content of D-SFSR register. |
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| 316 | */ |
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| 317 | static inline __u64 dtlb_sfsr_read(void) |
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| 318 | { |
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| 319 | return asi_u64_read(ASI_DMMU, VA_DMMU_SFSR); |
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| 320 | } |
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| 321 | |||
| 322 | /** Write DTLB Synchronous Fault Status Register. |
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| 323 | * |
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| 324 | * @param v New value of D-SFSR register. |
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| 325 | */ |
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| 326 | static inline void dtlb_sfsr_write(__u64 v) |
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| 327 | { |
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| 328 | asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v); |
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| 329 | flush(); |
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| 330 | } |
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| 331 | |||
| 332 | /** Read DTLB Synchronous Fault Address Register. |
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| 333 | * |
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| 334 | * @return Current content of D-SFAR register. |
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| 335 | */ |
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| 336 | static inline __u64 dtlb_sfar_read(void) |
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| 337 | { |
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| 338 | return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR); |
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| 339 | } |
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| 340 | |||
| 617 | jermar | 341 | /** Perform IMMU TLB Demap Operation. |
| 342 | * |
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| 343 | * @param type Selects between context and page demap. |
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| 344 | * @param context_encoding Specifies which Context register has Context ID for demap. |
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| 345 | * @param page Address which is on the page to be demapped. |
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| 346 | */ |
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| 347 | static inline void itlb_demap(int type, int context_encoding, __address page) |
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| 348 | { |
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| 349 | tlb_demap_addr_t da; |
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| 350 | page_address_t pg; |
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| 351 | |||
| 352 | da.value = 0; |
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| 353 | pg.address = page; |
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| 354 | |||
| 355 | da.type = type; |
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| 356 | da.context = context_encoding; |
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| 357 | da.vpn = pg.vpn; |
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| 358 | |||
| 359 | asi_u64_write(ASI_IMMU_DEMAP, da.value, 0); |
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| 360 | flush(); |
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| 361 | } |
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| 362 | |||
| 363 | /** Perform DMMU TLB Demap Operation. |
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| 364 | * |
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| 365 | * @param type Selects between context and page demap. |
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| 366 | * @param context_encoding Specifies which Context register has Context ID for demap. |
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| 367 | * @param page Address which is on the page to be demapped. |
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| 368 | */ |
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| 369 | static inline void dtlb_demap(int type, int context_encoding, __address page) |
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| 370 | { |
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| 371 | tlb_demap_addr_t da; |
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| 372 | page_address_t pg; |
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| 373 | |||
| 374 | da.value = 0; |
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| 375 | pg.address = page; |
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| 376 | |||
| 377 | da.type = type; |
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| 378 | da.context = context_encoding; |
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| 379 | da.vpn = pg.vpn; |
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| 380 | |||
| 381 | asi_u64_write(ASI_DMMU_DEMAP, da.value, 0); |
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| 382 | flush(); |
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| 383 | } |
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| 384 | |||
| 863 | jermar | 385 | extern void fast_instruction_access_mmu_miss(void); |
| 386 | extern void fast_data_access_mmu_miss(void); |
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| 387 | extern void fast_data_access_protection(void); |
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| 388 | |||
| 418 | jermar | 389 | #endif |