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| Rev | Author | Line No. | Line |
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| 418 | jermar | 1 | /* |
| 2 | * Copyright (C) 2005 Jakub Jermar |
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| 3 | * All rights reserved. |
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| 4 | * |
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| 5 | * Redistribution and use in source and binary forms, with or without |
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| 6 | * modification, are permitted provided that the following conditions |
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| 7 | * are met: |
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| 8 | * |
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| 9 | * - Redistributions of source code must retain the above copyright |
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| 10 | * notice, this list of conditions and the following disclaimer. |
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| 11 | * - Redistributions in binary form must reproduce the above copyright |
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| 12 | * notice, this list of conditions and the following disclaimer in the |
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| 13 | * documentation and/or other materials provided with the distribution. |
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| 14 | * - The name of the author may not be used to endorse or promote products |
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| 15 | * derived from this software without specific prior written permission. |
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| 16 | * |
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 27 | */ |
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| 28 | |||
| 29 | #ifndef __sparc64_ASM_H__ |
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| 30 | #define __sparc64_ASM_H__ |
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| 31 | |||
| 650 | jermar | 32 | #include <typedefs.h> |
| 418 | jermar | 33 | #include <arch/types.h> |
| 650 | jermar | 34 | #include <arch/register.h> |
| 418 | jermar | 35 | #include <config.h> |
| 36 | |||
| 650 | jermar | 37 | /** Read Processor State register. |
| 38 | * |
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| 39 | * @return Value of PSTATE register. |
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| 40 | */ |
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| 41 | static inline __u64 pstate_read(void) |
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| 42 | { |
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| 43 | __u64 v; |
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| 44 | |||
| 45 | __asm__ volatile ("rdpr %%pstate, %0\n" : "=r" (v)); |
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| 46 | |||
| 47 | return v; |
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| 48 | } |
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| 49 | |||
| 50 | /** Write Processor State register. |
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| 51 | * |
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| 52 | * @param New value of PSTATE register. |
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| 53 | */ |
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| 54 | static inline void pstate_write(__u64 v) |
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| 55 | { |
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| 56 | __asm__ volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0)); |
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| 57 | } |
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| 58 | |||
| 59 | |||
| 418 | jermar | 60 | /** Enable interrupts. |
| 61 | * |
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| 62 | * Enable interrupts and return previous |
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| 63 | * value of IPL. |
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| 64 | * |
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| 65 | * @return Old interrupt priority level. |
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| 66 | */ |
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| 67 | static inline ipl_t interrupts_enable(void) { |
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| 650 | jermar | 68 | pstate_reg_t pstate; |
| 69 | __u64 value; |
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| 70 | |||
| 71 | value = pstate_read(); |
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| 72 | pstate.value = value; |
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| 73 | pstate.ie = true; |
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| 74 | pstate_write(pstate.value); |
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| 75 | |||
| 76 | return (ipl_t) value; |
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| 418 | jermar | 77 | } |
| 78 | |||
| 79 | /** Disable interrupts. |
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| 80 | * |
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| 81 | * Disable interrupts and return previous |
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| 82 | * value of IPL. |
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| 83 | * |
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| 84 | * @return Old interrupt priority level. |
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| 85 | */ |
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| 86 | static inline ipl_t interrupts_disable(void) { |
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| 650 | jermar | 87 | pstate_reg_t pstate; |
| 88 | __u64 value; |
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| 89 | |||
| 90 | value = pstate_read(); |
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| 91 | pstate.value = value; |
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| 92 | pstate.ie = false; |
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| 93 | pstate_write(pstate.value); |
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| 94 | |||
| 95 | return (ipl_t) value; |
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| 418 | jermar | 96 | } |
| 97 | |||
| 98 | /** Restore interrupt priority level. |
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| 99 | * |
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| 100 | * Restore IPL. |
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| 101 | * |
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| 102 | * @param ipl Saved interrupt priority level. |
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| 103 | */ |
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| 104 | static inline void interrupts_restore(ipl_t ipl) { |
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| 650 | jermar | 105 | pstate_reg_t pstate; |
| 106 | |||
| 107 | pstate.value = pstate_read(); |
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| 108 | pstate.ie = ((pstate_reg_t) ipl).ie; |
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| 109 | pstate_write(pstate.value); |
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| 418 | jermar | 110 | } |
| 111 | |||
| 112 | /** Return interrupt priority level. |
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| 113 | * |
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| 114 | * Return IPL. |
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| 115 | * |
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| 116 | * @return Current interrupt priority level. |
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| 117 | */ |
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| 118 | static inline ipl_t interrupts_read(void) { |
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| 650 | jermar | 119 | return (ipl_t) pstate_read(); |
| 418 | jermar | 120 | } |
| 121 | |||
| 122 | /** Return base address of current stack. |
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| 123 | * |
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| 124 | * Return the base address of the current stack. |
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| 125 | * The stack is assumed to be STACK_SIZE bytes long. |
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| 126 | * The stack must start on page boundary. |
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| 127 | */ |
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| 128 | static inline __address get_stack_base(void) |
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| 129 | { |
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| 426 | jermar | 130 | __address v; |
| 131 | |||
| 650 | jermar | 132 | __asm__ volatile ("and %%sp, %1, %0\n" : "=r" (v) : "r" (~(STACK_SIZE-1))); |
| 426 | jermar | 133 | |
| 134 | return v; |
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| 418 | jermar | 135 | } |
| 136 | |||
| 640 | jermar | 137 | /** Read Version Register. |
| 138 | * |
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| 139 | * @return Value of VER register. |
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| 140 | */ |
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| 141 | static inline __u64 ver_read(void) |
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| 142 | { |
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| 143 | __u64 v; |
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| 144 | |||
| 145 | __asm__ volatile ("rdpr %%ver, %0\n" : "=r" (v)); |
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| 146 | |||
| 147 | return v; |
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| 148 | } |
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| 149 | |||
| 529 | jermar | 150 | /** Read Trap Base Address register. |
| 151 | * |
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| 152 | * @return Current value in TBA. |
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| 153 | */ |
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| 154 | static inline __u64 tba_read(void) |
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| 155 | { |
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| 156 | __u64 v; |
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| 157 | |||
| 158 | __asm__ volatile ("rdpr %%tba, %0\n" : "=r" (v)); |
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| 159 | |||
| 160 | return v; |
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| 161 | } |
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| 162 | |||
| 163 | /** Write Trap Base Address register. |
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| 164 | * |
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| 165 | * @param New value of TBA. |
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| 166 | */ |
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| 167 | static inline void tba_write(__u64 v) |
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| 168 | { |
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| 169 | __asm__ volatile ("wrpr %0, %1, %%tba\n" : : "r" (v), "i" (0)); |
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| 170 | } |
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| 171 | |||
| 569 | jermar | 172 | /** Load __u64 from alternate space. |
| 173 | * |
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| 174 | * @param asi ASI determining the alternate space. |
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| 175 | * @param va Virtual address within the ASI. |
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| 176 | * |
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| 177 | * @return Value read from the virtual address in the specified address space. |
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| 178 | */ |
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| 179 | static inline __u64 asi_u64_read(asi_t asi, __address va) |
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| 180 | { |
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| 181 | __u64 v; |
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| 182 | |||
| 183 | __asm__ volatile ("ldxa [%1] %2, %0\n" : "=r" (v) : "r" (va), "i" (asi)); |
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| 184 | |||
| 185 | return v; |
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| 186 | } |
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| 529 | jermar | 187 | |
| 569 | jermar | 188 | /** Store __u64 to alternate space. |
| 189 | * |
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| 190 | * @param asi ASI determining the alternate space. |
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| 191 | * @param va Virtual address within the ASI. |
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| 192 | * @param v Value to be written. |
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| 193 | */ |
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| 194 | static inline void asi_u64_write(asi_t asi, __address va, __u64 v) |
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| 195 | { |
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| 613 | jermar | 196 | __asm__ volatile ("stxa %0, [%1] %2\n" : : "r" (v), "r" (va), "i" (asi) : "memory"); |
| 569 | jermar | 197 | } |
| 198 | |||
| 418 | jermar | 199 | void cpu_halt(void); |
| 200 | void cpu_sleep(void); |
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| 201 | void asm_delay_loop(__u32 t); |
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| 202 | |||
| 203 | #endif |