Subversion Repositories HelenOS-historic

Rev

Rev 1780 | Details | Compare with Previous | Last modification | View Log | RSS feed

Rev Author Line No. Line
418 jermar 1
/*
2
 * Copyright (C) 2005 Jakub Jermar
3
 * All rights reserved.
4
 *
5
 * Redistribution and use in source and binary forms, with or without
6
 * modification, are permitted provided that the following conditions
7
 * are met:
8
 *
9
 * - Redistributions of source code must retain the above copyright
10
 *   notice, this list of conditions and the following disclaimer.
11
 * - Redistributions in binary form must reproduce the above copyright
12
 *   notice, this list of conditions and the following disclaimer in the
13
 *   documentation and/or other materials provided with the distribution.
14
 * - The name of the author may not be used to endorse or promote products
15
 *   derived from this software without specific prior written permission.
16
 *
17
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27
 */
28
 
1784 jermar 29
/** @addtogroup sparc64
1702 cejka 30
 * @{
31
 */
32
/** @file
33
 */
34
 
1784 jermar 35
#ifndef KERN_sparc64_ASM_H_
36
#define KERN_sparc64_ASM_H_
418 jermar 37
 
650 jermar 38
#include <typedefs.h>
418 jermar 39
#include <arch/types.h>
650 jermar 40
#include <arch/register.h>
418 jermar 41
#include <config.h>
42
 
650 jermar 43
/** Read Processor State register.
44
 *
45
 * @return Value of PSTATE register.
46
 */
1780 jermar 47
static inline uint64_t pstate_read(void)
650 jermar 48
{
1780 jermar 49
    uint64_t v;
650 jermar 50
 
51
    __asm__ volatile ("rdpr %%pstate, %0\n" : "=r" (v));
52
 
53
    return v;
54
}
55
 
56
/** Write Processor State register.
57
 *
1708 jermar 58
 * @param v New value of PSTATE register.
650 jermar 59
 */
1780 jermar 60
static inline void pstate_write(uint64_t v)
650 jermar 61
{
62
    __asm__ volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0));
63
}
64
 
658 jermar 65
/** Read TICK_compare Register.
66
 *
67
 * @return Value of TICK_comapre register.
68
 */
1780 jermar 69
static inline uint64_t tick_compare_read(void)
658 jermar 70
{
1780 jermar 71
    uint64_t v;
658 jermar 72
 
73
    __asm__ volatile ("rd %%tick_cmpr, %0\n" : "=r" (v));
74
 
75
    return v;
76
}
650 jermar 77
 
658 jermar 78
/** Write TICK_compare Register.
79
 *
1708 jermar 80
 * @param v New value of TICK_comapre register.
658 jermar 81
 */
1780 jermar 82
static inline void tick_compare_write(uint64_t v)
658 jermar 83
{
84
    __asm__ volatile ("wr %0, %1, %%tick_cmpr\n" : : "r" (v), "i" (0));
85
}
86
 
87
/** Read TICK Register.
88
 *
89
 * @return Value of TICK register.
90
 */
1780 jermar 91
static inline uint64_t tick_read(void)
658 jermar 92
{
1780 jermar 93
    uint64_t v;
658 jermar 94
 
95
    __asm__ volatile ("rdpr %%tick, %0\n" : "=r" (v));
96
 
97
    return v;
98
}
99
 
100
/** Write TICK Register.
101
 *
1708 jermar 102
 * @param v New value of TICK register.
658 jermar 103
 */
1780 jermar 104
static inline void tick_write(uint64_t v)
658 jermar 105
{
106
    __asm__ volatile ("wrpr %0, %1, %%tick\n" : : "r" (v), "i" (0));
107
}
108
 
664 jermar 109
/** Read SOFTINT Register.
110
 *
111
 * @return Value of SOFTINT register.
112
 */
1780 jermar 113
static inline uint64_t softint_read(void)
664 jermar 114
{
1780 jermar 115
    uint64_t v;
658 jermar 116
 
664 jermar 117
    __asm__ volatile ("rd %%softint, %0\n" : "=r" (v));
118
 
119
    return v;
120
}
121
 
122
/** Write SOFTINT Register.
123
 *
1708 jermar 124
 * @param v New value of SOFTINT register.
664 jermar 125
 */
1780 jermar 126
static inline void softint_write(uint64_t v)
664 jermar 127
{
128
    __asm__ volatile ("wr %0, %1, %%softint\n" : : "r" (v), "i" (0));
129
}
130
 
665 jermar 131
/** Write CLEAR_SOFTINT Register.
132
 *
133
 * Bits set in CLEAR_SOFTINT register will be cleared in SOFTINT register.
134
 *
1708 jermar 135
 * @param v New value of CLEAR_SOFTINT register.
665 jermar 136
 */
1780 jermar 137
static inline void clear_softint_write(uint64_t v)
665 jermar 138
{
139
    __asm__ volatile ("wr %0, %1, %%clear_softint\n" : : "r" (v), "i" (0));
140
}
141
 
418 jermar 142
/** Enable interrupts.
143
 *
144
 * Enable interrupts and return previous
145
 * value of IPL.
146
 *
147
 * @return Old interrupt priority level.
148
 */
149
static inline ipl_t interrupts_enable(void) {
650 jermar 150
    pstate_reg_t pstate;
1780 jermar 151
    uint64_t value;
650 jermar 152
 
153
    value = pstate_read();
154
    pstate.value = value;
155
    pstate.ie = true;
156
    pstate_write(pstate.value);
157
 
158
    return (ipl_t) value;
418 jermar 159
}
160
 
161
/** Disable interrupts.
162
 *
163
 * Disable interrupts and return previous
164
 * value of IPL.
165
 *
166
 * @return Old interrupt priority level.
167
 */
168
static inline ipl_t interrupts_disable(void) {
650 jermar 169
    pstate_reg_t pstate;
1780 jermar 170
    uint64_t value;
650 jermar 171
 
172
    value = pstate_read();
173
    pstate.value = value;
174
    pstate.ie = false;
175
    pstate_write(pstate.value);
176
 
177
    return (ipl_t) value;
418 jermar 178
}
179
 
180
/** Restore interrupt priority level.
181
 *
182
 * Restore IPL.
183
 *
184
 * @param ipl Saved interrupt priority level.
185
 */
186
static inline void interrupts_restore(ipl_t ipl) {
650 jermar 187
    pstate_reg_t pstate;
188
 
189
    pstate.value = pstate_read();
190
    pstate.ie = ((pstate_reg_t) ipl).ie;
191
    pstate_write(pstate.value);
418 jermar 192
}
193
 
194
/** Return interrupt priority level.
195
 *
196
 * Return IPL.
197
 *
198
 * @return Current interrupt priority level.
199
 */
200
static inline ipl_t interrupts_read(void) {
650 jermar 201
    return (ipl_t) pstate_read();
418 jermar 202
}
203
 
204
/** Return base address of current stack.
205
 *
206
 * Return the base address of the current stack.
207
 * The stack is assumed to be STACK_SIZE bytes long.
208
 * The stack must start on page boundary.
209
 */
1780 jermar 210
static inline uintptr_t get_stack_base(void)
418 jermar 211
{
1780 jermar 212
    uintptr_t v;
426 jermar 213
 
650 jermar 214
    __asm__ volatile ("and %%sp, %1, %0\n" : "=r" (v) : "r" (~(STACK_SIZE-1)));
426 jermar 215
 
216
    return v;
418 jermar 217
}
218
 
640 jermar 219
/** Read Version Register.
220
 *
221
 * @return Value of VER register.
222
 */
1780 jermar 223
static inline uint64_t ver_read(void)
640 jermar 224
{
1780 jermar 225
    uint64_t v;
640 jermar 226
 
227
    __asm__ volatile ("rdpr %%ver, %0\n" : "=r" (v));
228
 
229
    return v;
230
}
231
 
529 jermar 232
/** Read Trap Base Address register.
233
 *
234
 * @return Current value in TBA.
235
 */
1780 jermar 236
static inline uint64_t tba_read(void)
529 jermar 237
{
1780 jermar 238
    uint64_t v;
529 jermar 239
 
240
    __asm__ volatile ("rdpr %%tba, %0\n" : "=r" (v));
241
 
242
    return v;
243
}
244
 
873 jermar 245
/** Read Trap Program Counter register.
246
 *
247
 * @return Current value in TPC.
248
 */
1780 jermar 249
static inline uint64_t tpc_read(void)
873 jermar 250
{
1780 jermar 251
    uint64_t v;
873 jermar 252
 
253
    __asm__ volatile ("rdpr %%tpc, %0\n" : "=r" (v));
254
 
255
    return v;
256
}
257
 
883 jermar 258
/** Read Trap Level register.
259
 *
260
 * @return Current value in TL.
261
 */
1780 jermar 262
static inline uint64_t tl_read(void)
883 jermar 263
{
1780 jermar 264
    uint64_t v;
883 jermar 265
 
266
    __asm__ volatile ("rdpr %%tl, %0\n" : "=r" (v));
267
 
268
    return v;
269
}
873 jermar 270
 
529 jermar 271
/** Write Trap Base Address register.
272
 *
1708 jermar 273
 * @param v New value of TBA.
529 jermar 274
 */
1780 jermar 275
static inline void tba_write(uint64_t v)
529 jermar 276
{
277
    __asm__ volatile ("wrpr %0, %1, %%tba\n" : : "r" (v), "i" (0));
278
}
279
 
1780 jermar 280
/** Load uint64_t from alternate space.
569 jermar 281
 *
282
 * @param asi ASI determining the alternate space.
283
 * @param va Virtual address within the ASI.
284
 *
285
 * @return Value read from the virtual address in the specified address space.
286
 */
1780 jermar 287
static inline uint64_t asi_u64_read(asi_t asi, uintptr_t va)
569 jermar 288
{
1780 jermar 289
    uint64_t v;
569 jermar 290
 
291
    __asm__ volatile ("ldxa [%1] %2, %0\n" : "=r" (v) : "r" (va), "i" (asi));
292
 
293
    return v;
294
}
529 jermar 295
 
1780 jermar 296
/** Store uint64_t to alternate space.
569 jermar 297
 *
298
 * @param asi ASI determining the alternate space.
299
 * @param va Virtual address within the ASI.
300
 * @param v Value to be written.
301
 */
1780 jermar 302
static inline void asi_u64_write(asi_t asi, uintptr_t va, uint64_t v)
569 jermar 303
{
613 jermar 304
    __asm__ volatile ("stxa %0, [%1] %2\n" : :  "r" (v), "r" (va), "i" (asi) : "memory");
569 jermar 305
}
306
 
418 jermar 307
void cpu_halt(void);
308
void cpu_sleep(void);
1780 jermar 309
void asm_delay_loop(uint32_t t);
418 jermar 310
 
311
#endif
1702 cejka 312
 
1784 jermar 313
/** @}
1702 cejka 314
 */