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| 418 | jermar | 1 | /* |
| 2 | * Copyright (C) 2005 Jakub Jermar |
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| 3 | * All rights reserved. |
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| 4 | * |
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| 5 | * Redistribution and use in source and binary forms, with or without |
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| 6 | * modification, are permitted provided that the following conditions |
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| 7 | * are met: |
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| 8 | * |
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| 9 | * - Redistributions of source code must retain the above copyright |
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| 10 | * notice, this list of conditions and the following disclaimer. |
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| 11 | * - Redistributions in binary form must reproduce the above copyright |
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| 12 | * notice, this list of conditions and the following disclaimer in the |
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| 13 | * documentation and/or other materials provided with the distribution. |
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| 14 | * - The name of the author may not be used to endorse or promote products |
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| 15 | * derived from this software without specific prior written permission. |
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| 16 | * |
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 27 | */ |
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| 28 | |||
| 1702 | cejka | 29 | /** @addtogroup sparc64 |
| 30 | * @{ |
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| 31 | */ |
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| 32 | /** @file |
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| 33 | */ |
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| 34 | |||
| 418 | jermar | 35 | #ifndef __sparc64_ASM_H__ |
| 36 | #define __sparc64_ASM_H__ |
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| 37 | |||
| 650 | jermar | 38 | #include <typedefs.h> |
| 418 | jermar | 39 | #include <arch/types.h> |
| 650 | jermar | 40 | #include <arch/register.h> |
| 418 | jermar | 41 | #include <config.h> |
| 42 | |||
| 650 | jermar | 43 | /** Read Processor State register. |
| 44 | * |
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| 45 | * @return Value of PSTATE register. |
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| 46 | */ |
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| 47 | static inline __u64 pstate_read(void) |
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| 48 | { |
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| 49 | __u64 v; |
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| 50 | |||
| 51 | __asm__ volatile ("rdpr %%pstate, %0\n" : "=r" (v)); |
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| 52 | |||
| 53 | return v; |
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| 54 | } |
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| 55 | |||
| 56 | /** Write Processor State register. |
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| 57 | * |
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| 58 | * @param New value of PSTATE register. |
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| 59 | */ |
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| 60 | static inline void pstate_write(__u64 v) |
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| 61 | { |
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| 62 | __asm__ volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0)); |
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| 63 | } |
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| 64 | |||
| 658 | jermar | 65 | /** Read TICK_compare Register. |
| 66 | * |
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| 67 | * @return Value of TICK_comapre register. |
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| 68 | */ |
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| 69 | static inline __u64 tick_compare_read(void) |
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| 70 | { |
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| 71 | __u64 v; |
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| 72 | |||
| 73 | __asm__ volatile ("rd %%tick_cmpr, %0\n" : "=r" (v)); |
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| 74 | |||
| 75 | return v; |
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| 76 | } |
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| 650 | jermar | 77 | |
| 658 | jermar | 78 | /** Write TICK_compare Register. |
| 79 | * |
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| 80 | * @param New value of TICK_comapre register. |
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| 81 | */ |
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| 82 | static inline void tick_compare_write(__u64 v) |
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| 83 | { |
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| 84 | __asm__ volatile ("wr %0, %1, %%tick_cmpr\n" : : "r" (v), "i" (0)); |
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| 85 | } |
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| 86 | |||
| 87 | /** Read TICK Register. |
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| 88 | * |
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| 89 | * @return Value of TICK register. |
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| 90 | */ |
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| 91 | static inline __u64 tick_read(void) |
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| 92 | { |
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| 93 | __u64 v; |
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| 94 | |||
| 95 | __asm__ volatile ("rdpr %%tick, %0\n" : "=r" (v)); |
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| 96 | |||
| 97 | return v; |
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| 98 | } |
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| 99 | |||
| 100 | /** Write TICK Register. |
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| 101 | * |
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| 102 | * @param New value of TICK register. |
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| 103 | */ |
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| 104 | static inline void tick_write(__u64 v) |
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| 105 | { |
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| 106 | __asm__ volatile ("wrpr %0, %1, %%tick\n" : : "r" (v), "i" (0)); |
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| 107 | } |
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| 108 | |||
| 664 | jermar | 109 | /** Read SOFTINT Register. |
| 110 | * |
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| 111 | * @return Value of SOFTINT register. |
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| 112 | */ |
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| 113 | static inline __u64 softint_read(void) |
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| 114 | { |
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| 115 | __u64 v; |
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| 658 | jermar | 116 | |
| 664 | jermar | 117 | __asm__ volatile ("rd %%softint, %0\n" : "=r" (v)); |
| 118 | |||
| 119 | return v; |
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| 120 | } |
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| 121 | |||
| 122 | /** Write SOFTINT Register. |
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| 123 | * |
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| 124 | * @param New value of SOFTINT register. |
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| 125 | */ |
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| 126 | static inline void softint_write(__u64 v) |
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| 127 | { |
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| 128 | __asm__ volatile ("wr %0, %1, %%softint\n" : : "r" (v), "i" (0)); |
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| 129 | } |
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| 130 | |||
| 665 | jermar | 131 | /** Write CLEAR_SOFTINT Register. |
| 132 | * |
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| 133 | * Bits set in CLEAR_SOFTINT register will be cleared in SOFTINT register. |
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| 134 | * |
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| 135 | * @param New value of CLEAR_SOFTINT register. |
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| 136 | */ |
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| 137 | static inline void clear_softint_write(__u64 v) |
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| 138 | { |
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| 139 | __asm__ volatile ("wr %0, %1, %%clear_softint\n" : : "r" (v), "i" (0)); |
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| 140 | } |
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| 141 | |||
| 418 | jermar | 142 | /** Enable interrupts. |
| 143 | * |
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| 144 | * Enable interrupts and return previous |
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| 145 | * value of IPL. |
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| 146 | * |
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| 147 | * @return Old interrupt priority level. |
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| 148 | */ |
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| 149 | static inline ipl_t interrupts_enable(void) { |
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| 650 | jermar | 150 | pstate_reg_t pstate; |
| 151 | __u64 value; |
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| 152 | |||
| 153 | value = pstate_read(); |
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| 154 | pstate.value = value; |
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| 155 | pstate.ie = true; |
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| 156 | pstate_write(pstate.value); |
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| 157 | |||
| 158 | return (ipl_t) value; |
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| 418 | jermar | 159 | } |
| 160 | |||
| 161 | /** Disable interrupts. |
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| 162 | * |
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| 163 | * Disable interrupts and return previous |
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| 164 | * value of IPL. |
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| 165 | * |
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| 166 | * @return Old interrupt priority level. |
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| 167 | */ |
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| 168 | static inline ipl_t interrupts_disable(void) { |
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| 650 | jermar | 169 | pstate_reg_t pstate; |
| 170 | __u64 value; |
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| 171 | |||
| 172 | value = pstate_read(); |
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| 173 | pstate.value = value; |
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| 174 | pstate.ie = false; |
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| 175 | pstate_write(pstate.value); |
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| 176 | |||
| 177 | return (ipl_t) value; |
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| 418 | jermar | 178 | } |
| 179 | |||
| 180 | /** Restore interrupt priority level. |
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| 181 | * |
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| 182 | * Restore IPL. |
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| 183 | * |
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| 184 | * @param ipl Saved interrupt priority level. |
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| 185 | */ |
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| 186 | static inline void interrupts_restore(ipl_t ipl) { |
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| 650 | jermar | 187 | pstate_reg_t pstate; |
| 188 | |||
| 189 | pstate.value = pstate_read(); |
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| 190 | pstate.ie = ((pstate_reg_t) ipl).ie; |
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| 191 | pstate_write(pstate.value); |
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| 418 | jermar | 192 | } |
| 193 | |||
| 194 | /** Return interrupt priority level. |
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| 195 | * |
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| 196 | * Return IPL. |
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| 197 | * |
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| 198 | * @return Current interrupt priority level. |
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| 199 | */ |
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| 200 | static inline ipl_t interrupts_read(void) { |
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| 650 | jermar | 201 | return (ipl_t) pstate_read(); |
| 418 | jermar | 202 | } |
| 203 | |||
| 204 | /** Return base address of current stack. |
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| 205 | * |
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| 206 | * Return the base address of the current stack. |
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| 207 | * The stack is assumed to be STACK_SIZE bytes long. |
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| 208 | * The stack must start on page boundary. |
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| 209 | */ |
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| 210 | static inline __address get_stack_base(void) |
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| 211 | { |
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| 426 | jermar | 212 | __address v; |
| 213 | |||
| 650 | jermar | 214 | __asm__ volatile ("and %%sp, %1, %0\n" : "=r" (v) : "r" (~(STACK_SIZE-1))); |
| 426 | jermar | 215 | |
| 216 | return v; |
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| 418 | jermar | 217 | } |
| 218 | |||
| 640 | jermar | 219 | /** Read Version Register. |
| 220 | * |
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| 221 | * @return Value of VER register. |
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| 222 | */ |
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| 223 | static inline __u64 ver_read(void) |
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| 224 | { |
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| 225 | __u64 v; |
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| 226 | |||
| 227 | __asm__ volatile ("rdpr %%ver, %0\n" : "=r" (v)); |
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| 228 | |||
| 229 | return v; |
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| 230 | } |
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| 231 | |||
| 529 | jermar | 232 | /** Read Trap Base Address register. |
| 233 | * |
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| 234 | * @return Current value in TBA. |
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| 235 | */ |
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| 236 | static inline __u64 tba_read(void) |
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| 237 | { |
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| 238 | __u64 v; |
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| 239 | |||
| 240 | __asm__ volatile ("rdpr %%tba, %0\n" : "=r" (v)); |
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| 241 | |||
| 242 | return v; |
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| 243 | } |
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| 244 | |||
| 873 | jermar | 245 | /** Read Trap Program Counter register. |
| 246 | * |
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| 247 | * @return Current value in TPC. |
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| 248 | */ |
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| 249 | static inline __u64 tpc_read(void) |
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| 250 | { |
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| 251 | __u64 v; |
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| 252 | |||
| 253 | __asm__ volatile ("rdpr %%tpc, %0\n" : "=r" (v)); |
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| 254 | |||
| 255 | return v; |
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| 256 | } |
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| 257 | |||
| 883 | jermar | 258 | /** Read Trap Level register. |
| 259 | * |
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| 260 | * @return Current value in TL. |
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| 261 | */ |
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| 262 | static inline __u64 tl_read(void) |
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| 263 | { |
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| 264 | __u64 v; |
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| 265 | |||
| 266 | __asm__ volatile ("rdpr %%tl, %0\n" : "=r" (v)); |
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| 267 | |||
| 268 | return v; |
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| 269 | } |
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| 873 | jermar | 270 | |
| 529 | jermar | 271 | /** Write Trap Base Address register. |
| 272 | * |
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| 273 | * @param New value of TBA. |
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| 274 | */ |
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| 275 | static inline void tba_write(__u64 v) |
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| 276 | { |
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| 277 | __asm__ volatile ("wrpr %0, %1, %%tba\n" : : "r" (v), "i" (0)); |
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| 278 | } |
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| 279 | |||
| 569 | jermar | 280 | /** Load __u64 from alternate space. |
| 281 | * |
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| 282 | * @param asi ASI determining the alternate space. |
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| 283 | * @param va Virtual address within the ASI. |
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| 284 | * |
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| 285 | * @return Value read from the virtual address in the specified address space. |
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| 286 | */ |
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| 287 | static inline __u64 asi_u64_read(asi_t asi, __address va) |
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| 288 | { |
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| 289 | __u64 v; |
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| 290 | |||
| 291 | __asm__ volatile ("ldxa [%1] %2, %0\n" : "=r" (v) : "r" (va), "i" (asi)); |
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| 292 | |||
| 293 | return v; |
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| 294 | } |
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| 529 | jermar | 295 | |
| 569 | jermar | 296 | /** Store __u64 to alternate space. |
| 297 | * |
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| 298 | * @param asi ASI determining the alternate space. |
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| 299 | * @param va Virtual address within the ASI. |
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| 300 | * @param v Value to be written. |
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| 301 | */ |
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| 302 | static inline void asi_u64_write(asi_t asi, __address va, __u64 v) |
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| 303 | { |
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| 613 | jermar | 304 | __asm__ volatile ("stxa %0, [%1] %2\n" : : "r" (v), "r" (va), "i" (asi) : "memory"); |
| 569 | jermar | 305 | } |
| 306 | |||
| 658 | jermar | 307 | |
| 308 | |||
| 418 | jermar | 309 | void cpu_halt(void); |
| 310 | void cpu_sleep(void); |
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| 311 | void asm_delay_loop(__u32 t); |
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| 312 | |||
| 313 | #endif |
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| 1702 | cejka | 314 | |
| 315 | /** @} |
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| 316 | */ |
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| 317 |