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189 decky 1
/*
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 * Copyright (C) 2005 Martin Decky
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 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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342 jermar 29
#ifndef __ppc32_MACRO_H__
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#define __ppc32_MACRO_H__
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189 decky 32
/*
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 * PPC assembler macros
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 */
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/* Condition Register Bit Fields */
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#define cr0 0
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#define cr1 1
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#define cr2 2
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#define cr3 3
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#define cr4 4
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#define cr5 5
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#define cr6 6
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#define cr7 7
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/* General Purpose Registers (GPRs) */
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#define r0  0
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#define r1  1
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#define r2  2
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#define r3  3
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#define r4  4
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#define r5  5
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#define r6  6
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#define r7  7
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#define r8  8
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#define r9  9
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#define r10 10
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#define r11 11
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#define r12 12
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#define r13 13
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#define r14 14
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#define r15 15
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#define r16 16
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#define r17 17
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#define r18 18
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#define r19 19
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#define r20 20
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#define r21 21
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#define r22 22
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#define r23 23
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#define r24 24
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#define r25 25
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#define r26 26
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#define r27 27
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#define r28 28
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#define r29 29
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#define r30 30
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#define r31 31
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191 decky 80
/* GPR Aliases */
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#define sp  1
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189 decky 83
/* Floating Point Registers (FPRs) */
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#define fr0 0
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#define fr1 1
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#define fr2 2
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#define fr3 3
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#define fr4 4
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#define fr5 5
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#define fr6 6
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#define fr7 7
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#define fr8 8
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#define fr9 9
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#define fr10    10
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#define fr11    11
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#define fr12    12
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#define fr13    13
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#define fr14    14
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#define fr15    15
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#define fr16    16
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#define fr17    17
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#define fr18    18
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#define fr19    19
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#define fr20    20
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#define fr21    21
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#define fr22    22
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#define fr23    23
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#define fr24    24
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#define fr25    25
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#define fr26    26
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#define fr27    27
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#define fr28    28
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#define fr29    29
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#define fr30    30
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#define fr31    31
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#define vr0 0
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#define vr1 1
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#define vr2 2
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#define vr3 3
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#define vr4 4
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#define vr5 5
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#define vr6 6
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#define vr7 7
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#define vr8 8
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#define vr9 9
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#define vr10    10
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#define vr11    11
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#define vr12    12
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#define vr13    13
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#define vr14    14
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#define vr15    15
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#define vr16    16
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#define vr17    17
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#define vr18    18
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#define vr19    19
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#define vr20    20
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#define vr21    21
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#define vr22    22
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#define vr23    23
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#define vr24    24
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#define vr25    25
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#define vr26    26
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#define vr27    27
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#define vr28    28
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#define vr29    29
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#define vr30    30
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#define vr31    31
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#define evr0    0
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#define evr1    1
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#define evr2    2
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#define evr3    3
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#define evr4    4
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#define evr5    5
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#define evr6    6
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#define evr7    7
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#define evr8    8
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#define evr9    9
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#define evr10   10
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#define evr11   11
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#define evr12   12
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#define evr13   13
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#define evr14   14
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#define evr15   15
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#define evr16   16
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#define evr17   17
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#define evr18   18
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#define evr19   19
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#define evr20   20
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#define evr21   21
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#define evr22   22
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#define evr23   23
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#define evr24   24
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#define evr25   25
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#define evr26   26
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#define evr27   27
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#define evr28   28
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#define evr29   29
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#define evr30   30
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#define evr31   31
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/* Special Purpose Registers (SPRs) */
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#define xer 1
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#define lr  8
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#define ctr 9
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#define dec 22
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#define srr0    26
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#define srr1    27
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#define sprg0   272
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#define sprg1   273
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#define sprg2   274
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#define sprg3   275
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#define prv 287
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.macro REGISTERS_STORE r
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    stw r0, 0(\r)
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    stw r1, 4(\r)
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    stw r2, 8(\r)
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    stw r3, 12(\r)
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    stw r4, 16(\r)
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    stw r5, 20(\r)
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    stw r6, 24(\r)
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    stw r7, 28(\r)
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    stw r8, 32(\r)
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    stw r9, 36(\r)
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    stw r10, 40(\r)
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    stw r11, 44(\r)
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    stw r12, 48(\r)
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    stw r13, 52(\r)
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    stw r14, 56(\r)
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    stw r15, 60(\r)
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    stw r16, 64(\r)
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    stw r17, 68(\r)
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    stw r18, 72(\r)
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    stw r19, 76(\r)
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    stw r20, 80(\r)
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    stw r21, 84(\r)
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    stw r22, 88(\r)
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    stw r23, 92(\r)
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    stw r24, 96(\r)
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    stw r25, 100(\r)
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    stw r26, 104(\r)
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    stw r27, 108(\r)
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    stw r28, 112(\r)
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    stw r29, 116(\r)
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    stw r30, 120(\r)
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    stw r31, 124(\r)
189 decky 229
.endm
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.macro REGISTERS_LOAD r
199 decky 232
    lwz r0, 0(\r)
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    lwz r1, 4(\r)
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    lwz r2, 8(\r)  
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    lwz r3, 12(\r)
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    lwz r4, 16(\r)
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    lwz r5, 20(\r)
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    lwz r6, 24(\r)
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    lwz r7, 28(\r)
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    lwz r8, 32(\r)
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    lwz r9, 36(\r)
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    lwz r10, 40(\r)
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    lwz r11, 44(\r)
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    lwz r12, 48(\r)
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    lwz r13, 52(\r)
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    lwz r14, 56(\r)
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    lwz r15, 60(\r)
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    lwz r16, 64(\r)
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    lwz r17, 68(\r)
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    lwz r18, 72(\r)
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    lwz r19, 76(\r)
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    lwz r20, 80(\r)
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    lwz r21, 84(\r)
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    lwz r22, 88(\r)
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    lwz r23, 92(\r)
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    lwz r24, 96(\r)
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    lwz r25, 100(\r)
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    lwz r26, 104(\r)
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    lwz r27, 108(\r)
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    lwz r28, 112(\r)
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    lwz r29, 116(\r)
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    lwz r30, 120(\r)
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    lwz r31, 124(\r)
189 decky 264
.endm
342 jermar 265
 
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#endif