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| Rev | Author | Line No. | Line |
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| 1 | jermar | 1 | /* |
| 2 | * Copyright (C) 2001-2004 Jakub Jermar |
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| 3 | * All rights reserved. |
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| 4 | * |
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| 5 | * Redistribution and use in source and binary forms, with or without |
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| 6 | * modification, are permitted provided that the following conditions |
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| 7 | * are met: |
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| 8 | * |
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| 9 | * - Redistributions of source code must retain the above copyright |
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| 10 | * notice, this list of conditions and the following disclaimer. |
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| 11 | * - Redistributions in binary form must reproduce the above copyright |
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| 12 | * notice, this list of conditions and the following disclaimer in the |
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| 13 | * documentation and/or other materials provided with the distribution. |
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| 14 | * - The name of the author may not be used to endorse or promote products |
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| 15 | * derived from this software without specific prior written permission. |
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| 16 | * |
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 27 | */ |
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| 28 | |||
| 29 | #include <arch/cpu.h> |
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| 30 | #include <cpu.h> |
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| 31 | |||
| 32 | #include <arch.h> |
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| 33 | |||
| 34 | #include <arch/cp0.h> |
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| 35 | |||
| 36 | #include <typedefs.h> |
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| 37 | |||
| 38 | struct { |
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| 39 | char *vendor; |
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| 40 | char *model; |
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| 41 | } imp_data[] = { |
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| 42 | { "Invalid", "Invalid" }, /* 0x00 */ |
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| 43 | { "MIPS", "R2000" }, /* 0x01 */ |
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| 44 | { "MIPS", "R3000" }, /* 0x02 */ |
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| 45 | { "MIPS", "R6000" }, /* 0x03 */ |
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| 46 | { "MIPS", " R4000/R4400" }, /* 0x04 */ |
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| 47 | { "LSI Logic", "R3000" }, /* 0x05 */ |
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| 48 | { "MIPS", "R6000A" }, /* 0x06 */ |
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| 49 | { "IDT", "3051/3052" }, /* 0x07 */ |
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| 50 | { "Invalid", "Invalid" }, /* 0x08 */ |
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| 51 | { "MIPS", "R10000/T5" }, /* 0x09 */ |
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| 52 | { "MIPS", "R4200" }, /* 0x0a */ |
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| 53 | { "Unknown", "Unknown" }, /* 0x0b */ |
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| 54 | { "Unknown", "Unknown" }, /* 0x0c */ |
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| 55 | { "Invalid", "Invalid" }, /* 0x0d */ |
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| 56 | { "Invalid", "Invalid" }, /* 0x0e */ |
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| 57 | { "Invalid", "Invalid" }, /* 0x0f */ |
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| 58 | { "MIPS", "R8000" }, /* 0x10 */ |
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| 59 | { "Invalid", "Invalid" }, /* 0x11 */ |
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| 60 | { "Invalid", "Invalid" }, /* 0x12 */ |
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| 61 | { "Invalid", "Invalid" }, /* 0x13 */ |
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| 62 | { "Invalid", "Invalid" }, /* 0x14 */ |
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| 63 | { "Invalid", "Invalid" }, /* 0x15 */ |
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| 64 | { "Invalid", "Invalid" }, /* 0x16 */ |
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| 65 | { "Invalid", "Invalid" }, /* 0x17 */ |
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| 66 | { "Invalid", "Invalid" }, /* 0x18 */ |
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| 67 | { "Invalid", "Invalid" }, /* 0x19 */ |
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| 68 | { "Invalid", "Invalid" }, /* 0x1a */ |
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| 69 | { "Invalid", "Invalid" }, /* 0x1b */ |
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| 70 | { "Invalid", "Invalid" }, /* 0x1c */ |
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| 71 | { "Invalid", "Invalid" }, /* 0x1d */ |
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| 72 | { "Invalid", "Invalid" }, /* 0x1e */ |
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| 73 | { "Invalid", "Invalid" }, /* 0x1f */ |
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| 74 | { "QED", "R4600" }, /* 0x20 */ |
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| 75 | { "Sony", "R3000" }, /* 0x21 */ |
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| 76 | { "Toshiba", "R3000" }, /* 0x22 */ |
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| 77 | { "NKK", "R3000" } /* 0x23 */ |
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| 78 | }; |
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| 79 | |||
| 80 | void cpu_arch_init(void) |
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| 81 | { |
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| 82 | } |
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| 83 | |||
| 84 | void cpu_identify(void) |
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| 85 | { |
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| 86 | the->cpu->arch.rev_num = cp0_prid_read() & 0xff; |
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| 87 | the->cpu->arch.imp_num = (cp0_prid_read() >> 8) & 0xff; |
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| 88 | } |
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| 89 | |||
| 90 | void cpu_print_report(cpu_t *m) |
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| 91 | { |
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| 92 | printf("cpu%d: %s %s (rev=%d.%d, imp=%d)\n", |
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| 93 | m->id, imp_data[m->arch.imp_num].vendor, imp_data[m->arch.imp_num].model, m->arch.rev_num >> 4, m->arch.rev_num & 0xf, m->arch.imp_num); |
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| 94 | } |