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1 jermar 1
#
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# Copyright (C) 2003-2004 Jakub Jermar
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions
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# are met:
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#
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# - Redistributions of source code must retain the above copyright
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#   notice, this list of conditions and the following disclaimer.
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# - Redistributions in binary form must reproduce the above copyright
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#   notice, this list of conditions and the following disclaimer in the
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#   documentation and/or other materials provided with the distribution.
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# - The name of the author may not be used to endorse or promote products
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#   derived from this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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326 palkovsky 29
#include <arch/asm/regname.h>
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.text
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.macro cp0_read reg
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	mfc0 $2,\reg
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	j $31
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	nop
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.endm
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.macro cp0_write reg
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	mtc0 $4,\reg
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	j $31
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	nop
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.endm
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.set noat
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.set noreorder
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.set nomacro
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.global cpu_halt
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cpu_halt:
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	j cpu_halt
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	nop
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.global memsetb
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memsetb:
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	j _memsetb
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	nop
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.global memcpy
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.global memcpy_from_uspace
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.global memcpy_to_uspace
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.global memcpy_from_uspace_failover_address
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.global memcpy_to_uspace_failover_address
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memcpy:
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memcpy_from_uspace:
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memcpy_to_uspace:
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        srl     $t1,$a2,0x2
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	beqz    $t1,1f
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        move    $t0,$zero
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        move    $a3,$zero
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2:	
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        addu    $v0,$a1,$a3
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        lw      $v1,0($v0)
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        addiu   $t0,$t0,1
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        addu    $v0,$a0,$a3
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        sw      $v1,0($v0)
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        bne     $t0,$t1,2b
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        addiu   $a3,$a3,4
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1:	
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        andi    $a2,$a2,0x3
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        beqz    $a2,3f
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        move    $a3,$zero
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        sll     $v0,$t0,0x2
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        addu    $t1,$a0,$v0
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        addu    $t0,$v0,$a1
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4:	
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        addu    $v0,$t0,$a3
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        lbu     $a0,0($v0)
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        addu    $v1,$t1,$a3
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        addiu   $a3,$a3,1
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        bne     $a3,$a2,4b
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        sb      $a0,0($v1)
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3:	
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        jr      $ra
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        move    $v0,$a1
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1288 jermar 99
memcpy_from_uspace_failover_address:
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memcpy_to_uspace_failover_address:
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	jr	$ra
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	move	$v0, $zero
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326 palkovsky 106
.macro fpu_gp_save reg ctx
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	mfc1 $t0,$\reg
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	sw $t0, \reg*4(\ctx)
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.endm
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.macro fpu_gp_restore reg ctx
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	lw $t0, \reg*4(\ctx)
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	mtc1 $t0,$\reg
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.endm
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.macro fpu_ct_save reg ctx
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	cfc1 $t0,$1
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	sw $t0, (\reg+32)*4(\ctx)
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.endm	
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.macro fpu_ct_restore reg ctx
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	lw $t0, (\reg+32)*4(\ctx)
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	ctc1 $t0,$\reg
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.endm
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.global fpu_context_save
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fpu_context_save:
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#ifdef ARCH_HAS_FPU
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	fpu_gp_save 0,$a0
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	fpu_gp_save 1,$a0
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	fpu_gp_save 2,$a0
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	fpu_gp_save 3,$a0
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	fpu_gp_save 4,$a0
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	fpu_gp_save 5,$a0
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	fpu_gp_save 6,$a0
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	fpu_gp_save 7,$a0
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	fpu_gp_save 8,$a0
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	fpu_gp_save 9,$a0
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	fpu_gp_save 10,$a0
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	fpu_gp_save 11,$a0
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	fpu_gp_save 12,$a0
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	fpu_gp_save 13,$a0
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	fpu_gp_save 14,$a0
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	fpu_gp_save 15,$a0
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	fpu_gp_save 16,$a0
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	fpu_gp_save 17,$a0
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	fpu_gp_save 18,$a0
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	fpu_gp_save 19,$a0
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	fpu_gp_save 20,$a0
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	fpu_gp_save 21,$a0
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	fpu_gp_save 22,$a0
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	fpu_gp_save 23,$a0
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	fpu_gp_save 24,$a0
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	fpu_gp_save 25,$a0
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	fpu_gp_save 26,$a0
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	fpu_gp_save 27,$a0
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	fpu_gp_save 28,$a0
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	fpu_gp_save 29,$a0
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	fpu_gp_save 30,$a0
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	fpu_gp_save 31,$a0
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	fpu_ct_save 1,$a0
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	fpu_ct_save 2,$a0
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	fpu_ct_save 3,$a0
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	fpu_ct_save 4,$a0
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	fpu_ct_save 5,$a0
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	fpu_ct_save 6,$a0
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	fpu_ct_save 7,$a0
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	fpu_ct_save 8,$a0
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	fpu_ct_save 9,$a0
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	fpu_ct_save 10,$a0
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	fpu_ct_save 11,$a0
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	fpu_ct_save 12,$a0
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	fpu_ct_save 13,$a0
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	fpu_ct_save 14,$a0
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	fpu_ct_save 15,$a0
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	fpu_ct_save 16,$a0
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	fpu_ct_save 17,$a0
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	fpu_ct_save 18,$a0
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	fpu_ct_save 19,$a0
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	fpu_ct_save 20,$a0
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	fpu_ct_save 21,$a0
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	fpu_ct_save 22,$a0
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	fpu_ct_save 23,$a0
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	fpu_ct_save 24,$a0
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	fpu_ct_save 25,$a0
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	fpu_ct_save 26,$a0
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	fpu_ct_save 27,$a0
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	fpu_ct_save 28,$a0
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	fpu_ct_save 29,$a0
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	fpu_ct_save 30,$a0
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	fpu_ct_save 31,$a0
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#endif		
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	j $ra
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	nop
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198
.global fpu_context_restore
199
fpu_context_restore:
924 palkovsky 200
#ifdef ARCH_HAS_FPU
326 palkovsky 201
	fpu_gp_restore 0,$a0
202
	fpu_gp_restore 1,$a0
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	fpu_gp_restore 2,$a0
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	fpu_gp_restore 3,$a0
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	fpu_gp_restore 4,$a0
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	fpu_gp_restore 5,$a0
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	fpu_gp_restore 6,$a0
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	fpu_gp_restore 7,$a0
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	fpu_gp_restore 8,$a0
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	fpu_gp_restore 9,$a0
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	fpu_gp_restore 10,$a0
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	fpu_gp_restore 11,$a0
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	fpu_gp_restore 12,$a0
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	fpu_gp_restore 13,$a0
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	fpu_gp_restore 14,$a0
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	fpu_gp_restore 15,$a0
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	fpu_gp_restore 16,$a0
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	fpu_gp_restore 17,$a0
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	fpu_gp_restore 18,$a0
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	fpu_gp_restore 19,$a0
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	fpu_gp_restore 20,$a0
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	fpu_gp_restore 21,$a0
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	fpu_gp_restore 22,$a0
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	fpu_gp_restore 23,$a0
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	fpu_gp_restore 24,$a0
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	fpu_gp_restore 25,$a0
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	fpu_gp_restore 26,$a0
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	fpu_gp_restore 27,$a0
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	fpu_gp_restore 28,$a0
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	fpu_gp_restore 29,$a0
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	fpu_gp_restore 30,$a0
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	fpu_gp_restore 31,$a0
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234
	fpu_ct_restore 1,$a0
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	fpu_ct_restore 2,$a0
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	fpu_ct_restore 3,$a0
237
	fpu_ct_restore 4,$a0
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	fpu_ct_restore 5,$a0
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	fpu_ct_restore 6,$a0
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	fpu_ct_restore 7,$a0
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	fpu_ct_restore 8,$a0
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	fpu_ct_restore 9,$a0
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	fpu_ct_restore 10,$a0
244
	fpu_ct_restore 11,$a0
245
	fpu_ct_restore 12,$a0
246
	fpu_ct_restore 13,$a0
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	fpu_ct_restore 14,$a0
248
	fpu_ct_restore 15,$a0
249
	fpu_ct_restore 16,$a0
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	fpu_ct_restore 17,$a0
251
	fpu_ct_restore 18,$a0
252
	fpu_ct_restore 19,$a0
253
	fpu_ct_restore 20,$a0
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	fpu_ct_restore 21,$a0
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	fpu_ct_restore 22,$a0
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	fpu_ct_restore 23,$a0
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	fpu_ct_restore 24,$a0
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	fpu_ct_restore 25,$a0
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	fpu_ct_restore 26,$a0
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	fpu_ct_restore 27,$a0
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	fpu_ct_restore 28,$a0
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	fpu_ct_restore 29,$a0
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	fpu_ct_restore 30,$a0
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	fpu_ct_restore 31,$a0
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#endif	
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	j $ra
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	nop