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/*
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 * Copyright (C) 2003-2004 Jakub Jermar
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 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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#ifndef __mips32_CP0_H__
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#define __mips32_CP0_H__
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#include <arch/types.h>
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#define cp0_status_ie_enabled_bit   (1<<0)
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#define cp0_status_exl_exception_bit    (1<<1)
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#define cp0_status_erl_error_bit    (1<<2)
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#define cp0_status_um_bit           (1<<4)
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#define cp0_status_bev_bootstrap_bit    (1<<22)
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#define cp0_status_fpu_bit              (1<<29)
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#define cp0_status_im_shift     8
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#define cp0_status_im_mask              0xff00
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#define cp0_cause_excno(cause) ((cause >> 2) & 0x1f)
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#define cp0_cause_coperr(cause) ((cause >> 28) & 0x3)
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#define fpu_cop_id 1
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/*
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 * Magic value for use in msim.
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 * On AMD Duron 800Mhz, this roughly seems like one us.
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 */
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#define cp0_compare_value       10000
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static inline void tlbp(void)
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{
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    __asm__ volatile ("tlbp");
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}
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static inline void tlbr(void)
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{
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    __asm__ volatile ("tlbr");
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}
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static inline void tlbwi(void)
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{
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    __asm__ volatile ("tlbwi");
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}
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static inline void tlbwr(void)
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{
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    __asm__ volatile ("tlbwr");
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}
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#define cp0_mask_all_int() cp0_status_write(cp0_status_read() & ~(cp0_status_im_mask))
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#define cp0_unmask_all_int() cp0_status_write(cp0_status_read() | cp0_status_im_mask)
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#define cp0_mask_int(it) cp0_status_write(cp0_status_read() & ~(1<<(cp0_status_im_shift+(it))))
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#define cp0_unmask_int(it) cp0_status_write(cp0_status_read() | (1<<(cp0_status_im_shift+(it))))
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extern  __u32 cp0_index_read(void);
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extern void cp0_idnex_write(__u32 val);
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extern __u32 cp0_random_read(void);
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extern __u32 cp0_entry_lo0_read(void);
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extern void cp0_entry_lo0_write(__u32 val);
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extern __u32 cp0_entry_lo1_read(void);
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extern void cp0_entry_lo1_write(__u32 val);
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extern __u32 cp0_context_read(void);
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extern void cp0_context_write(__u32 val);
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extern __u32 cp0_pagemask_read(void);
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extern void cp0_pagemask_write(__u32 val);
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extern __u32 cp0_wired_read(void);
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extern void cp0_wired_write(__u32 val);
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extern __u32 cp0_badvaddr_read(void);
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extern volatile __u32 cp0_count_read(void);
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extern void cp0_count_write(__u32 val);
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extern volatile __u32 cp0_entry_hi_read(void);
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extern void cp0_entry_hi_write(__u32 val);
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extern volatile __u32 cp0_compare_read(void);
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extern void cp0_compare_write(__u32 val);
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extern __u32 cp0_status_read(void);
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extern void cp0_status_write(__u32 val);
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extern __u32 cp0_cause_read(void);
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extern void cp0_cause_write(__u32 val);
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extern __u32 cp0_epc_read(void);
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extern void cp0_epc_write(__u32 val);
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extern __u32 cp0_prid_read(void);
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#endif