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/*
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 * Copyright (C) 2003-2004 Jakub Jermar
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 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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/** @addtogroup mips32
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 * @{
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 */
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/** @file
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 */
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#ifndef __mips32_CP0_H__
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#define __mips32_CP0_H__
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#include <arch/types.h>
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#include <arch/mm/tlb.h>
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#define cp0_status_ie_enabled_bit   (1<<0)
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#define cp0_status_exl_exception_bit    (1<<1)
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#define cp0_status_erl_error_bit    (1<<2)
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#define cp0_status_um_bit           (1<<4)
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#define cp0_status_bev_bootstrap_bit    (1<<22)
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#define cp0_status_fpu_bit              (1<<29)
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#define cp0_status_im_shift     8
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#define cp0_status_im_mask              0xff00
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#define cp0_cause_excno(cause) ((cause >> 2) & 0x1f)
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#define cp0_cause_coperr(cause) ((cause >> 28) & 0x3)
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#define fpu_cop_id 1
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/*
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 * Magic value for use in msim.
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 */
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#define cp0_compare_value       100000
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#define cp0_mask_all_int() cp0_status_write(cp0_status_read() & ~(cp0_status_im_mask))
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#define cp0_unmask_all_int() cp0_status_write(cp0_status_read() | cp0_status_im_mask)
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#define cp0_mask_int(it) cp0_status_write(cp0_status_read() & ~(1<<(cp0_status_im_shift+(it))))
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#define cp0_unmask_int(it) cp0_status_write(cp0_status_read() | (1<<(cp0_status_im_shift+(it))))
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#define GEN_READ_CP0(nm,reg) static inline uint32_t cp0_ ##nm##_read(void) \
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  { \
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      uint32_t retval; \
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      asm("mfc0 %0, $" #reg : "=r"(retval)); \
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      return retval; \
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  }
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#define GEN_WRITE_CP0(nm,reg) static inline void cp0_ ##nm##_write(uint32_t val) \
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 { \
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    asm("mtc0 %0, $" #reg : : "r"(val) ); \
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 }
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GEN_READ_CP0(index, 0);
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GEN_WRITE_CP0(index, 0);
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GEN_READ_CP0(random, 1);
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GEN_READ_CP0(entry_lo0, 2);
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GEN_WRITE_CP0(entry_lo0, 2);
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GEN_READ_CP0(entry_lo1, 3);
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GEN_WRITE_CP0(entry_lo1, 3);
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GEN_READ_CP0(context, 4);
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GEN_WRITE_CP0(context, 4);
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GEN_READ_CP0(pagemask, 5);
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GEN_WRITE_CP0(pagemask, 5);
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GEN_READ_CP0(wired, 6);
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GEN_WRITE_CP0(wired, 6);
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GEN_READ_CP0(badvaddr, 8);
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GEN_READ_CP0(count, 9);
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GEN_WRITE_CP0(count, 9);
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GEN_READ_CP0(entry_hi, 10);
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GEN_WRITE_CP0(entry_hi, 10);
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GEN_READ_CP0(compare, 11);
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GEN_WRITE_CP0(compare, 11);
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GEN_READ_CP0(status, 12);
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GEN_WRITE_CP0(status, 12);
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GEN_READ_CP0(cause, 13);
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GEN_WRITE_CP0(cause, 13);
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GEN_READ_CP0(epc, 14);
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GEN_WRITE_CP0(epc, 14);
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GEN_READ_CP0(prid, 15);
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#endif
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/** @}
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 */