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/*
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 * Copyright (C) 2005 Ondrej Palkovsky
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 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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#ifndef __mips32_ATOMIC_H__
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#define __mips32_ATOMIC_H__
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#include <arch/types.h>
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#define atomic_inc(x)   (a_add(x,1))
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#define atomic_dec(x)   (a_sub(x,1))
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#define atomic_inc_pre(x) (a_add(x,1)-1)
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#define atomic_dec_pre(x) (a_sub(x,1)+1)
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#define atomic_inc_post(x) (a_add(x,1))
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#define atomic_dec_post(x) (a_sub(x,1))
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typedef volatile __u32 atomic_t;
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/*
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 * Atomic addition
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 *
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 * This case is harder, and we have to use the special LL and SC operations
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 * to achieve atomicity. The instructions are similar to LW (load) and SW
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 * (store), except that the LL (load-linked) instruction loads the address
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 * of the variable to a special register and if another process writes to
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 * the same location, the SC (store-conditional) instruction fails.
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 Returns (*val)+i
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 */
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static inline atomic_t a_add(atomic_t *val, int i)
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{
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    atomic_t tmp, tmp2;
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    asm volatile (
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        "   .set    push\n"
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        "   .set    noreorder\n"
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        "   nop\n"
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        "1:\n"
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        "   ll  %0, %1\n"
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        "   addu    %0, %0, %3\n"
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        "       move    %2, %0\n"
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        "   sc  %0, %1\n"
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        "   beq %0, 0x0, 1b\n"
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        "   move    %0, %2\n"
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        "   .set    pop\n"
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        : "=&r" (tmp), "=o" (*val), "=r" (tmp2)
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        : "r" (i)
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        );
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    return tmp;
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}
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/*
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 * Atomic subtraction
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 *
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 * Implemented in the same manner as a_add, except we substract the value.
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 Returns (*val)-i
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 */
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static inline atomic_t a_sub(atomic_t *val, int i)
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{
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    atomic_t tmp, tmp2;
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    asm volatile (
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        "   .set    push\n"
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        "   .set    noreorder\n"
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        "   nop\n"
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        "1:\n"
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        "   ll  %0, %1\n"
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        "   subu    %0, %0, %3\n"
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        "       move    %2, %0\n"
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        "   sc  %0, %1\n"
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        "   beq %0, 0x0, 1b\n"
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        "       move    %0, %2\n"
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        "   .set    pop\n"
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        : "=&r" (tmp), "=o" (*val), "=r" (tmp2)
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        : "r" (i)
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        );
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    return tmp;
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}
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#endif