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212 vana 1
#
2
# Copyright (C) 2005 Jakub Vana
3
# All rights reserved.
4
#
5
# Redistribution and use in source and binary forms, with or without
6
# modification, are permitted provided that the following conditions
7
# are met:
8
#
9
# - Redistributions of source code must retain the above copyright
10
#   notice, this list of conditions and the following disclaimer.
11
# - Redistributions in binary form must reproduce the above copyright
12
#   notice, this list of conditions and the following disclaimer in the
13
#   documentation and/or other materials provided with the distribution.
14
# - The name of the author may not be used to endorse or promote products
15
#   derived from this software without specific prior written permission.
16
#
17
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27
#
28
 
443 jermar 29
#include <arch/stack.h>
212 vana 30
 
443 jermar 31
#define STACK_ITEMS		12
32
#define STACK_FRAME_SIZE	((STACK_ITEMS*STACK_ITEM_SIZE) + STACK_SCRATCH_AREA_SIZE)
33
 
34
#if (STACK_FRAME_SIZE % STACK_ALIGNMENT != 0)
35
#error Memory stack must be 16-byte aligned.
36
#endif
37
 
438 jermar 38
/** Heavyweight interrupt handler
39
 *
435 jermar 40
 * This macro roughly follows steps from 1 to 19 described in
41
 * Intel Itanium Architecture Software Developer's Manual, Chapter 3.4.2.
42
 *
438 jermar 43
 * HEAVYWEIGHT_HANDLER macro must cram into 16 bundles (48 instructions).
44
 * This goal is achieved by using procedure calls after RSE becomes operational.
45
 *
435 jermar 46
 * Some steps are skipped (enabling and disabling interrupts).
47
 * Some steps are not fully supported yet (e.g. interruptions
438 jermar 48
 * from userspace and floating-point context).
435 jermar 49
 */
50
.macro HEAVYWEIGHT_HANDLER offs handler
51
    .org IVT + \offs
212 vana 52
 
435 jermar 53
    /* 1. copy interrupt registers into bank 0 */
54
	mov r24 = cr.iip
55
	mov r25 = cr.ipsr
56
	mov r26 = cr.iipa
57
	mov r27 = cr.isr
58
	mov r28 = cr.ifa
59
 
60
    /* 2. preserve predicate register into bank 0 */
61
	mov r29 = pr ;;
62
 
438 jermar 63
    /* 3. switch to kernel memory stack */
435 jermar 64
	/* TODO: support interruptions from userspace */
65
	/* assume kernel stack */
66
 
439 jermar 67
    /* 4. save registers in bank 0 into memory stack */
443 jermar 68
	add r31 = -8, r12 ;;
69
	add r12 = -STACK_FRAME_SIZE, r12 ;;
441 jermar 70
 
443 jermar 71
	st8 [r31] = r29, -8 ;;	/* save predicate registers */
438 jermar 72
 
443 jermar 73
	st8 [r31] = r24, -8 ;;	/* save cr.iip */
74
	st8 [r31] = r25, -8 ;;	/* save cr.ipsr */
75
	st8 [r31] = r26, -8 ;;	/* save cr.iipa */
76
	st8 [r31] = r27, -8 ;;	/* save cr.isr */
77
	st8 [r31] = r28, -8 ;;	/* save cr.ifa */		
438 jermar 78
 
79
    /* 5. RSE switch from interrupted context */
435 jermar 80
    	.auto
81
	mov r24 = ar.rsc
82
	mov r25 = ar.pfs
83
	cover
84
	mov r26 = cr.ifs
85
 
443 jermar 86
	st8 [r31] = r24, -8	/* save ar.rsc */
87
	st8 [r31] = r25, -8	/* save ar.pfs */
88
	st8 [r31] = r26, -8	/* save ar.ifs */
435 jermar 89
 
90
	and r30 = ~3, r24
91
	mov ar.rsc = r30	/* place RSE in enforced lazy mode */
92
 
93
	mov r27 = ar.rnat
94
	mov r28 = ar.bspstore
95
 
96
	/* assume kernel backing store */
97
	mov ar.bspstore = r28
98
 
99
	mov r29 = ar.bsp
100
 
443 jermar 101
	st8 [r31] = r27, -8	/* save ar.rnat */
102
	st8 [r31] = r28, -8	/* save ar.bspstore */
103
	st8 [r31] = r29		/* save ar.bsp */
435 jermar 104
 
105
	mov ar.rsc = r24	/* restore RSE's setting */
106
	.explicit
107
 
438 jermar 108
    /* the rest of the save-handler can be kept outside IVT */
109
 
110
	movl r24 = \handler
111
	mov r25 = b0
112
	br.call.sptk.many rp = heavyweight_handler_inner
113
0:	mov b0 = r25	
114
 
439 jermar 115
	br heavyweight_handler_finalize
438 jermar 116
.endm
117
 
118
.global heavyweight_handler_inner
119
heavyweight_handler_inner:
120
	/*
121
	 * From this point, the rest of the interrupted context
122
	 * will be preserved in stacked registers and backing store.
123
	 */
124
	alloc loc0 = ar.pfs, 0, 46, 0, 0 ;;
125
 
126
	/* copy handler address (r24 from bank 0 will be invisible soon) */
127
	mov loc1 = r24
128
 
435 jermar 129
    /* 6. switch to bank 1 and reenable PSR.ic */
130
	ssm 0x2000
131
	bsw.1 ;;
132
	srlz.d
133
 
134
    /* 7. preserve branch and application registers */
438 jermar 135
    	mov loc2 = ar.unat
136
	mov loc3 = ar.lc
137
	mov loc4 = ar.ec
138
	mov loc5 = ar.ccv
139
	mov loc6 = ar.csd
140
	mov loc7 = ar.ssd
435 jermar 141
 
438 jermar 142
	mov loc8 = b0
143
	mov loc9 = b1
144
	mov loc10 = b2
145
	mov loc11 = b3
146
	mov loc12 = b4
147
	mov loc13 = b5
148
	mov loc14 = b6
149
	mov loc15 = b7
150
 
435 jermar 151
    /* 8. preserve general and floating-point registers */
152
	/* TODO: save floating-point context */
438 jermar 153
	mov loc16 = r1
154
	mov loc17 = r2
155
	mov loc18 = r3
156
	mov loc19 = r4
157
	mov loc20 = r5
158
	mov loc21 = r6
159
	mov loc22 = r7
160
	mov loc23 = r8
161
	mov loc24 = r9
162
	mov loc25 = r10
163
	mov loc26 = r11
164
	/* skip r12 (stack pointer) */
165
	mov loc27 = r13
166
	mov loc28 = r14
167
	mov loc29 = r15
168
	mov loc30 = r16
169
	mov loc31 = r17
170
	mov loc32 = r18
171
	mov loc33 = r19
172
	mov loc34 = r20
173
	mov loc35 = r21
174
	mov loc36 = r22
175
	mov loc37 = r23
176
	mov loc38 = r24
177
	mov loc39 = r25
178
	mov loc40 = r26
179
	mov loc41 = r27
180
	mov loc42 = r28
181
	mov loc43 = r29
182
	mov loc44 = r30
183
	mov loc45 = r31
184
 
435 jermar 185
    /* 9. skipped (will not enable interrupts) */
238 vana 186
 
438 jermar 187
    /* 10. call handler */
188
    	mov b1 = loc1
189
	br.call.sptk.many b0 = b1
190
 
191
    /* 11. return from handler */
192
0:
193
 
435 jermar 194
    /* 12. skipped (will not disable interrupts) */
438 jermar 195
 
435 jermar 196
    /* 13. restore general and floating-point registers */
197
	/* TODO: restore floating-point context */
438 jermar 198
	mov r1 = loc16
199
	mov r2 = loc17
200
	mov r3 = loc18
201
	mov r4 = loc19
202
	mov r5 = loc20
203
	mov r6 = loc21
204
	mov r7 = loc22
205
	mov r8 = loc23
206
	mov r9 = loc24
207
	mov r10 = loc25
208
	mov r11 = loc26
209
	/* skip r12 (stack pointer) */
210
	mov r13 = loc27
211
	mov r14 = loc28
212
	mov r15 = loc29
213
	mov r16 = loc30
214
	mov r17 = loc31
215
	mov r18 = loc32
216
	mov r19 = loc33
217
	mov r20 = loc34
218
	mov r21 = loc35
219
	mov r22 = loc36
220
	mov r23 = loc37
221
	mov r24 = loc38
222
	mov r25 = loc39
223
	mov r26 = loc40
224
	mov r27 = loc41
225
	mov r28 = loc42
226
	mov r29 = loc43
227
	mov r30 = loc44
228
	mov r31 = loc45
435 jermar 229
 
230
    /* 14. restore branch and application registers */
438 jermar 231
    	mov ar.unat = loc2
232
	mov ar.lc = loc3
233
	mov ar.ec = loc4
234
	mov ar.ccv = loc5
235
	mov ar.csd = loc6
236
	mov ar.ssd = loc7
435 jermar 237
 
438 jermar 238
	mov b0 = loc8
239
	mov b1 = loc9
240
	mov b2 = loc10
241
	mov b3 = loc11
242
	mov b4 = loc12
243
	mov b5 = loc13
244
	mov b6 = loc14
245
	mov b7 = loc15
246
 
435 jermar 247
    /* 15. disable PSR.ic and switch to bank 0 */
248
	rsm 0x2000
249
	bsw.0 ;;
250
	srlz.d
438 jermar 251
 
252
	mov ar.pfs = loc0
253
	br.ret.sptk.many rp
254
 
255
.global heavyweight_handler_finalize
256
heavyweight_handler_finalize:
257
    /* 16. RSE switch to interrupted context */
435 jermar 258
 
259
    /* 17. restore interruption state from memory stack */
260
 
261
    /* 18. restore predicate registers from memory stack */
262
 
263
    /* 19. return from interruption */
264
	rfi
265
 
266
 
438 jermar 267
 
268
 
238 vana 269
dump_gregs:
270
mov r16 = REG_DUMP;;
271
st8 [r16] = r0;;
272
add r16 = 8,r16 ;;
273
st8 [r16] = r1;;
274
add r16 = 8,r16 ;;
275
st8 [r16] = r2;;
276
add r16 = 8,r16 ;;
277
st8 [r16] = r3;;
278
add r16 = 8,r16 ;;
279
st8 [r16] = r4;;
280
add r16 = 8,r16 ;;
281
st8 [r16] = r5;;
282
add r16 = 8,r16 ;;
283
st8 [r16] = r6;;
284
add r16 = 8,r16 ;;
285
st8 [r16] = r7;;
286
add r16 = 8,r16 ;;
287
st8 [r16] = r8;;
288
add r16 = 8,r16 ;;
289
st8 [r16] = r9;;
290
add r16 = 8,r16 ;;
291
st8 [r16] = r10;;
292
add r16 = 8,r16 ;;
293
st8 [r16] = r11;;
294
add r16 = 8,r16 ;;
295
st8 [r16] = r12;;
296
add r16 = 8,r16 ;;
297
st8 [r16] = r13;;
298
add r16 = 8,r16 ;;
299
st8 [r16] = r14;;
300
add r16 = 8,r16 ;;
301
st8 [r16] = r15;;
302
add r16 = 8,r16 ;;
303
 
304
bsw.1;;
305
mov r15 = r16;;
306
bsw.0;;
307
st8 [r16] = r15;;
308
add r16 = 8,r16 ;;
309
bsw.1;;
310
mov r15 = r17;;
311
bsw.0;;
312
st8 [r16] = r15;;
313
add r16 = 8,r16 ;;
314
bsw.1;;
315
mov r15 = r18;;
316
bsw.0;;
317
st8 [r16] = r15;;
318
add r16 = 8,r16 ;;
319
bsw.1;;
320
mov r15 = r19;;
321
bsw.0;;
322
st8 [r16] = r15;;
323
add r16 = 8,r16 ;;
324
bsw.1;;
325
mov r15 = r20;;
326
bsw.0;;
327
st8 [r16] = r15;;
328
add r16 = 8,r16 ;;
329
bsw.1;;
330
mov r15 = r21;;
331
bsw.0;;
332
st8 [r16] = r15;;
333
add r16 = 8,r16 ;;
334
bsw.1;;
335
mov r15 = r22;;
336
bsw.0;;
337
st8 [r16] = r15;;
338
add r16 = 8,r16 ;;
339
bsw.1;;
340
mov r15 = r23;;
341
bsw.0;;
342
st8 [r16] = r15;;
343
add r16 = 8,r16 ;;
344
bsw.1;;
345
mov r15 = r24;;
346
bsw.0;;
347
st8 [r16] = r15;;
348
add r16 = 8,r16 ;;
349
bsw.1;;
350
mov r15 = r25;;
351
bsw.0;;
352
st8 [r16] = r15;;
353
add r16 = 8,r16 ;;
354
bsw.1;;
355
mov r15 = r26;;
356
bsw.0;;
357
st8 [r16] = r15;;
358
add r16 = 8,r16 ;;
359
bsw.1;;
360
mov r15 = r27;;
361
bsw.0;;
362
st8 [r16] = r15;;
363
add r16 = 8,r16 ;;
364
bsw.1;;
365
mov r15 = r28;;
366
bsw.0;;
367
st8 [r16] = r15;;
368
add r16 = 8,r16 ;;
369
bsw.1;;
370
mov r15 = r29;;
371
bsw.0;;
372
st8 [r16] = r15;;
373
add r16 = 8,r16 ;;
374
bsw.1;;
375
mov r15 = r30;;
376
bsw.0;;
377
st8 [r16] = r15;;
378
add r16 = 8,r16 ;;
379
bsw.1;;
380
mov r15 = r31;;
381
bsw.0;;
382
st8 [r16] = r15;;
383
add r16 = 8,r16 ;;
384
 
385
 
386
st8 [r16] = r32;;
387
add r16 = 8,r16 ;;
388
st8 [r16] = r33;;
389
add r16 = 8,r16 ;;
390
st8 [r16] = r34;;
391
add r16 = 8,r16 ;;
392
st8 [r16] = r35;;
393
add r16 = 8,r16 ;;
394
st8 [r16] = r36;;
395
add r16 = 8,r16 ;;
396
st8 [r16] = r37;;
397
add r16 = 8,r16 ;;
398
st8 [r16] = r38;;
399
add r16 = 8,r16 ;;
400
st8 [r16] = r39;;
401
add r16 = 8,r16 ;;
402
st8 [r16] = r40;;
403
add r16 = 8,r16 ;;
404
st8 [r16] = r41;;
405
add r16 = 8,r16 ;;
406
st8 [r16] = r42;;
407
add r16 = 8,r16 ;;
408
st8 [r16] = r43;;
409
add r16 = 8,r16 ;;
410
st8 [r16] = r44;;
411
add r16 = 8,r16 ;;
412
st8 [r16] = r45;;
413
add r16 = 8,r16 ;;
414
st8 [r16] = r46;;
415
add r16 = 8,r16 ;;
416
st8 [r16] = r47;;
417
add r16 = 8,r16 ;;
418
st8 [r16] = r48;;
419
add r16 = 8,r16 ;;
420
st8 [r16] = r49;;
421
add r16 = 8,r16 ;;
422
st8 [r16] = r50;;
423
add r16 = 8,r16 ;;
424
st8 [r16] = r51;;
425
add r16 = 8,r16 ;;
426
st8 [r16] = r52;;
427
add r16 = 8,r16 ;;
428
st8 [r16] = r53;;
429
add r16 = 8,r16 ;;
430
st8 [r16] = r54;;
431
add r16 = 8,r16 ;;
432
st8 [r16] = r55;;
433
add r16 = 8,r16 ;;
434
st8 [r16] = r56;;
435
add r16 = 8,r16 ;;
436
st8 [r16] = r57;;
437
add r16 = 8,r16 ;;
438
st8 [r16] = r58;;
439
add r16 = 8,r16 ;;
440
st8 [r16] = r59;;
441
add r16 = 8,r16 ;;
442
st8 [r16] = r60;;
443
add r16 = 8,r16 ;;
444
st8 [r16] = r61;;
445
add r16 = 8,r16 ;;
446
st8 [r16] = r62;;
447
add r16 = 8,r16 ;;
448
st8 [r16] = r63;;
449
add r16 = 8,r16 ;;
450
 
451
 
452
 
453
st8 [r16] = r64;;
454
add r16 = 8,r16 ;;
455
st8 [r16] = r65;;
456
add r16 = 8,r16 ;;
457
st8 [r16] = r66;;
458
add r16 = 8,r16 ;;
459
st8 [r16] = r67;;
460
add r16 = 8,r16 ;;
461
st8 [r16] = r68;;
462
add r16 = 8,r16 ;;
463
st8 [r16] = r69;;
464
add r16 = 8,r16 ;;
465
st8 [r16] = r70;;
466
add r16 = 8,r16 ;;
467
st8 [r16] = r71;;
468
add r16 = 8,r16 ;;
469
st8 [r16] = r72;;
470
add r16 = 8,r16 ;;
471
st8 [r16] = r73;;
472
add r16 = 8,r16 ;;
473
st8 [r16] = r74;;
474
add r16 = 8,r16 ;;
475
st8 [r16] = r75;;
476
add r16 = 8,r16 ;;
477
st8 [r16] = r76;;
478
add r16 = 8,r16 ;;
479
st8 [r16] = r77;;
480
add r16 = 8,r16 ;;
481
st8 [r16] = r78;;
482
add r16 = 8,r16 ;;
483
st8 [r16] = r79;;
484
add r16 = 8,r16 ;;
485
st8 [r16] = r80;;
486
add r16 = 8,r16 ;;
487
st8 [r16] = r81;;
488
add r16 = 8,r16 ;;
489
st8 [r16] = r82;;
490
add r16 = 8,r16 ;;
491
st8 [r16] = r83;;
492
add r16 = 8,r16 ;;
493
st8 [r16] = r84;;
494
add r16 = 8,r16 ;;
495
st8 [r16] = r85;;
496
add r16 = 8,r16 ;;
497
st8 [r16] = r86;;
498
add r16 = 8,r16 ;;
499
st8 [r16] = r87;;
500
add r16 = 8,r16 ;;
501
st8 [r16] = r88;;
502
add r16 = 8,r16 ;;
503
st8 [r16] = r89;;
504
add r16 = 8,r16 ;;
505
st8 [r16] = r90;;
506
add r16 = 8,r16 ;;
507
st8 [r16] = r91;;
508
add r16 = 8,r16 ;;
509
st8 [r16] = r92;;
510
add r16 = 8,r16 ;;
511
st8 [r16] = r93;;
512
add r16 = 8,r16 ;;
513
st8 [r16] = r94;;
514
add r16 = 8,r16 ;;
515
st8 [r16] = r95;;
516
add r16 = 8,r16 ;;
517
 
518
 
519
 
520
st8 [r16] = r96;;
521
add r16 = 8,r16 ;;
522
st8 [r16] = r97;;
523
add r16 = 8,r16 ;;
524
st8 [r16] = r98;;
525
add r16 = 8,r16 ;;
526
st8 [r16] = r99;;
527
add r16 = 8,r16 ;;
528
st8 [r16] = r100;;
529
add r16 = 8,r16 ;;
530
st8 [r16] = r101;;
531
add r16 = 8,r16 ;;
532
st8 [r16] = r102;;
533
add r16 = 8,r16 ;;
534
st8 [r16] = r103;;
535
add r16 = 8,r16 ;;
536
st8 [r16] = r104;;
537
add r16 = 8,r16 ;;
538
st8 [r16] = r105;;
539
add r16 = 8,r16 ;;
540
st8 [r16] = r106;;
541
add r16 = 8,r16 ;;
542
st8 [r16] = r107;;
543
add r16 = 8,r16 ;;
544
st8 [r16] = r108;;
545
add r16 = 8,r16 ;;
546
st8 [r16] = r109;;
547
add r16 = 8,r16 ;;
548
st8 [r16] = r110;;
549
add r16 = 8,r16 ;;
550
st8 [r16] = r111;;
551
add r16 = 8,r16 ;;
552
st8 [r16] = r112;;
553
add r16 = 8,r16 ;;
554
st8 [r16] = r113;;
555
add r16 = 8,r16 ;;
556
st8 [r16] = r114;;
557
add r16 = 8,r16 ;;
558
st8 [r16] = r115;;
559
add r16 = 8,r16 ;;
560
st8 [r16] = r116;;
561
add r16 = 8,r16 ;;
562
st8 [r16] = r117;;
563
add r16 = 8,r16 ;;
564
st8 [r16] = r118;;
565
add r16 = 8,r16 ;;
566
st8 [r16] = r119;;
567
add r16 = 8,r16 ;;
568
st8 [r16] = r120;;
569
add r16 = 8,r16 ;;
570
st8 [r16] = r121;;
571
add r16 = 8,r16 ;;
572
st8 [r16] = r122;;
573
add r16 = 8,r16 ;;
574
st8 [r16] = r123;;
575
add r16 = 8,r16 ;;
576
st8 [r16] = r124;;
577
add r16 = 8,r16 ;;
578
st8 [r16] = r125;;
579
add r16 = 8,r16 ;;
580
st8 [r16] = r126;;
581
add r16 = 8,r16 ;;
582
st8 [r16] = r127;;
583
add r16 = 8,r16 ;;
584
 
585
 
586
 
587
br.ret.sptk.many b0;;
588
 
589
 
590
 
591
 
592
 
212 vana 593
.macro Handler o h
594
.org IVT + \o
595
br \h;;
596
.endm
597
 
220 vana 598
.macro Handler2 o 
599
.org IVT + \o
238 vana 600
br.call.sptk.many b0 = dump_gregs;;
601
mov r16 = \o ;;
602
bsw.1;;
220 vana 603
br universal_handler;;
604
.endm
212 vana 605
 
606
 
220 vana 607
 
212 vana 608
.global IVT
609
.align 32768
610
IVT:
611
 
220 vana 612
 
613
Handler2 0x0000
614
Handler2 0x0400
615
Handler2 0x0800
616
Handler2 0x0c00
617
Handler2 0x1000
618
Handler2 0x1400
619
Handler2 0x1800
620
Handler2 0x1c00
621
Handler2 0x2000
622
Handler2 0x2400
623
Handler2 0x2800
212 vana 624
Handler 0x2c00 break_instruction
435 jermar 625
HEAVYWEIGHT_HANDLER 0x3000 external_interrupt	/* For external interrupt, heavyweight handler is used. */
220 vana 626
Handler2 0x3400
627
Handler2 0x3800
628
Handler2 0x3c00
629
Handler2 0x4000
630
Handler2 0x4400
631
Handler2 0x4800
632
Handler2 0x4c00
633
 
634
Handler2 0x5000
635
Handler2 0x5100
636
Handler2 0x5200
637
Handler2 0x5300
238 vana 638
#Handler 0x5400 general_exception
639
Handler2 0x5400
220 vana 640
Handler2 0x5500
641
Handler2 0x5600
642
Handler2 0x5700
643
Handler2 0x5800
644
Handler2 0x5900
645
Handler2 0x5a00
646
Handler2 0x5b00
647
Handler2 0x5c00
648
Handler2 0x5d00
649
Handler2 0x5e00
650
Handler2 0x5f00
212 vana 651
 
220 vana 652
Handler2 0x6000
653
Handler2 0x6100
654
Handler2 0x6200
655
Handler2 0x6300
656
Handler2 0x6400
657
Handler2 0x6500
658
Handler2 0x6600
659
Handler2 0x6700
660
Handler2 0x6800
661
Handler2 0x6900
662
Handler2 0x6a00
663
Handler2 0x6b00
664
Handler2 0x6c00
665
Handler2 0x6d00
666
Handler2 0x6e00
667
Handler2 0x6f00
212 vana 668
 
220 vana 669
Handler2 0x7000
670
Handler2 0x7100
671
Handler2 0x7200
672
Handler2 0x7300
673
Handler2 0x7400
674
Handler2 0x7500
675
Handler2 0x7600
676
Handler2 0x7700
677
Handler2 0x7800
678
Handler2 0x7900
679
Handler2 0x7a00
680
Handler2 0x7b00
681
Handler2 0x7c00
682
Handler2 0x7d00
683
Handler2 0x7e00
684
Handler2 0x7f00
212 vana 685
 
686
 
220 vana 687
 
688
 
689
 
690
 
691
 
692
 
212 vana 693
.align 32768
238 vana 694
.global REG_DUMP
695
 
696
REG_DUMP:
697
.space 128*8
698