Subversion Repositories HelenOS-historic

Rev

Rev 1023 | Rev 1056 | Go to most recent revision | Details | Compare with Previous | Last modification | View Log | RSS feed

Rev Author Line No. Line
212 vana 1
#
2
# Copyright (C) 2005 Jakub Vana
478 jermar 3
# Copyright (C) 2005 Jakub Jermar
212 vana 4
# All rights reserved.
5
#
6
# Redistribution and use in source and binary forms, with or without
7
# modification, are permitted provided that the following conditions
8
# are met:
9
#
10
# - Redistributions of source code must retain the above copyright
11
#   notice, this list of conditions and the following disclaimer.
12
# - Redistributions in binary form must reproduce the above copyright
13
#   notice, this list of conditions and the following disclaimer in the
14
#   documentation and/or other materials provided with the distribution.
15
# - The name of the author may not be used to endorse or promote products
16
#   derived from this software without specific prior written permission.
17
#
18
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28
#
29
 
443 jermar 30
#include <arch/stack.h>
478 jermar 31
#include <arch/register.h>
912 jermar 32
#include <arch/mm/page.h>
33
#include <align.h>
212 vana 34
 
1053 vana 35
 
36
#define FRS_TO_SAVE 30
37
#define STACK_ITEMS		(19 + FRS_TO_SAVE*2)
38
//#define STACK_ITEMS		19 		
39
	/* 30*2 for FPU registers */
912 jermar 40
#define STACK_FRAME_SIZE	ALIGN_UP((STACK_ITEMS*STACK_ITEM_SIZE) + STACK_SCRATCH_AREA_SIZE, STACK_ALIGNMENT)
443 jermar 41
 
912 jermar 42
#if (STACK_ITEMS % 2 == 0)
43
#	define STACK_FRAME_BIAS	8
44
#else
45
#	define STACK_FRAME_BIAS 16
443 jermar 46
#endif
47
 
911 jermar 48
/** Partitioning of bank 0 registers. */
49
#define R_OFFS 		r16
50
#define R_HANDLER	r17
51
#define R_RET		r18
921 jermar 52
#define R_TMP		r19
916 jermar 53
#define R_KSTACK_BSP	r22	/* keep in sync with before_thread_runs_arch() */
911 jermar 54
#define R_KSTACK	r23	/* keep in sync with before_thread_runs_arch() */
55
 
438 jermar 56
/** Heavyweight interrupt handler
57
 *
435 jermar 58
 * This macro roughly follows steps from 1 to 19 described in
59
 * Intel Itanium Architecture Software Developer's Manual, Chapter 3.4.2.
60
 *
438 jermar 61
 * HEAVYWEIGHT_HANDLER macro must cram into 16 bundles (48 instructions).
62
 * This goal is achieved by using procedure calls after RSE becomes operational.
63
 *
435 jermar 64
 * Some steps are skipped (enabling and disabling interrupts).
916 jermar 65
 * Some steps are not fully supported yet (e.g. dealing with floating-point
66
 * context).
456 jermar 67
 *
68
 * @param offs Offset from the beginning of IVT.
69
 * @param handler Interrupt handler address.
435 jermar 70
 */
470 jermar 71
.macro HEAVYWEIGHT_HANDLER offs, handler=universal_handler
72
    .org ivt + \offs
911 jermar 73
	mov R_OFFS = \offs
74
	movl R_HANDLER = \handler ;;
470 jermar 75
	br heavyweight_handler
76
.endm
212 vana 77
 
470 jermar 78
.global heavyweight_handler
79
heavyweight_handler:
435 jermar 80
    /* 1. copy interrupt registers into bank 0 */
911 jermar 81
 
82
	/*
912 jermar 83
	 * Note that r24-r31 from bank 0 can be used only as long as PSR.ic = 0.
911 jermar 84
	 */
1053 vana 85
 
86
			/*Set up FPU as in interrupred*/
87
	mov r24=psr
88
	mov r25=cr.ipsr 
89
	mov r26=(PSR_DFH_MASK)
90
	mov r27=(~(PSR_DFH_MASK));;
91
	and r26=r25,r26
92
	and r24=r24,r27;;
93
	or r24=r24,r26;;
94
	mov psr.l=r24;;
95
	srlz.i
96
	srlz.d;;
97
 
435 jermar 98
	mov r24 = cr.iip
99
	mov r25 = cr.ipsr
100
	mov r26 = cr.iipa
101
	mov r27 = cr.isr
102
	mov r28 = cr.ifa
103
 
104
    /* 2. preserve predicate register into bank 0 */
105
	mov r29 = pr ;;
106
 
438 jermar 107
    /* 3. switch to kernel memory stack */
912 jermar 108
    	mov r30 = cr.ipsr
916 jermar 109
	shr.u r31 = r12, VRN_SHIFT ;;
912 jermar 110
 
916 jermar 111
	shr.u r30 = r30, PSR_CPL_SHIFT ;;
112
	and r30 = PSR_CPL_MASK_SHIFTED, r30 ;;
113
 
912 jermar 114
	/*
916 jermar 115
	 * Set p3 to true if the interrupted context executed in kernel mode.
116
	 * Set p4 to false if the interrupted context didn't execute in kernel mode.
912 jermar 117
	 */
916 jermar 118
	cmp.eq p3, p4 = r30, r0 ;;
119
	cmp.eq p1, p2 = r30, r0 ;;	/* remember IPSR setting in p1 and p2 */
912 jermar 120
 
121
	/*
916 jermar 122
	 * Set p3 to true if the stack register references kernel address space.
123
	 * Set p4 to false if the stack register doesn't reference kernel address space.
912 jermar 124
	 */
921 jermar 125
(p3)	cmp.eq p3, p4 = VRN_KERNEL, r31 ;;
912 jermar 126
 
127
	/*
916 jermar 128
	 * Now, p4 is true iff the stack needs to be switched to kernel stack.
912 jermar 129
	 */
130
	mov r30 = r12
921 jermar 131
(p4)	mov r12 = R_KSTACK ;;
912 jermar 132
 
133
	add r31 = -STACK_FRAME_BIAS, r12 ;;
470 jermar 134
	add r12 = -STACK_FRAME_SIZE, r12
135
 
921 jermar 136
    /* 4. save registers in bank 0 into memory stack */
137
 
138
	/*
139
	 * If this is break_instruction handler,
140
	 * copy input parameters to stack.
141
	 */
142
    	mov R_TMP = 0x2c00 ;;
143
	cmp.eq p6,p5 = R_OFFS, R_TMP ;;
144
 
145
	/*
146
	 * From now on, if this is break_instruction handler, p6 is true and p5 is false.
147
	 * Otherwise p6 is false and p5 is true.
148
	 * Note that p5 is a preserved predicate register and we make use of it.
149
	 */
962 jermar 150
 
151
(p6)	st8 [r31] = r36, -8 ;;		/* save in4 */	
921 jermar 152
(p6)	st8 [r31] = r35, -8 ;;		/* save in3 */
153
(p6) 	st8 [r31] = r34, -8 ;;		/* save in2 */
154
(p6)	st8 [r31] = r33, -8 ;;		/* save in1 */
155
(p6)	st8 [r31] = r32, -8 ;;		/* save in0 */
962 jermar 156
(p5)	add r31 = -40, r31 ;;
921 jermar 157
 
912 jermar 158
	st8 [r31] = r30, -8 ;;		/* save old stack pointer */ 
159
 
160
	st8 [r31] = r29, -8 ;;		/* save predicate registers */
438 jermar 161
 
912 jermar 162
	st8 [r31] = r24, -8 ;;		/* save cr.iip */
163
	st8 [r31] = r25, -8 ;;		/* save cr.ipsr */
164
	st8 [r31] = r26, -8 ;;		/* save cr.iipa */
165
	st8 [r31] = r27, -8 ;;		/* save cr.isr */
166
	st8 [r31] = r28, -8 ;;		/* save cr.ifa */
438 jermar 167
 
168
    /* 5. RSE switch from interrupted context */
435 jermar 169
	mov r24 = ar.rsc
170
	mov r25 = ar.pfs
171
	cover
172
	mov r26 = cr.ifs
173
 
916 jermar 174
	st8 [r31] = r24, -8 ;;		/* save ar.rsc */
175
	st8 [r31] = r25, -8 ;;		/* save ar.pfs */
176
	st8 [r31] = r26, -8		/* save ar.ifs */
435 jermar 177
 
919 jermar 178
	and r24 = ~(RSC_PL_MASK), r24 ;;
179
	and r30 = ~(RSC_MODE_MASK), r24 ;;
180
	mov ar.rsc = r30 ;;		/* update RSE state */
435 jermar 181
 
182
	mov r27 = ar.rnat
470 jermar 183
	mov r28 = ar.bspstore ;;
435 jermar 184
 
916 jermar 185
	/*
186
	 * Inspect BSPSTORE to figure out whether it is necessary to switch to kernel BSPSTORE.
187
	 */
921 jermar 188
(p1)	shr.u r30 = r28, VRN_SHIFT ;;
189
(p1)	cmp.eq p1, p2 = VRN_KERNEL, r30 ;;
435 jermar 190
 
916 jermar 191
	/*
192
	 * If BSPSTORE needs to be switched, p1 is false and p2 is true.
193
	 */
921 jermar 194
(p1)	mov r30 = r28
195
(p2)	mov r30 = R_KSTACK_BSP ;;
196
(p2)	mov ar.bspstore = r30 ;;
916 jermar 197
 
435 jermar 198
	mov r29 = ar.bsp
199
 
916 jermar 200
	st8 [r31] = r27, -8 ;;		/* save ar.rnat */
201
	st8 [r31] = r30, -8 ;;		/* save new value written to ar.bspstore */
202
	st8 [r31] = r28, -8 ;;		/* save ar.bspstore */
203
	st8 [r31] = r29, -8 		/* save ar.bsp */
435 jermar 204
 
919 jermar 205
	mov ar.rsc = r24		/* restore RSE's setting + kernel privileges */
435 jermar 206
 
470 jermar 207
    /* steps 6 - 15 are done by heavyweight_handler_inner() */
916 jermar 208
	mov R_RET = b0 			/* save b0 belonging to interrupted context */
911 jermar 209
	br.call.sptk.many b0 = heavyweight_handler_inner
916 jermar 210
0:	mov b0 = R_RET			/* restore b0 belonging to the interrupted context */
438 jermar 211
 
470 jermar 212
    /* 16. RSE switch to interrupted context */
916 jermar 213
	cover				/* allocate zerro size frame (step 1 (from Intel Docs)) */
438 jermar 214
 
1053 vana 215
	add r31 = (STACK_SCRATCH_AREA_SIZE+(FRS_TO_SAVE*2*8)), r12 ;;
470 jermar 216
 
915 jermar 217
	ld8 r30 = [r31], +8 ;;		/* load ar.bsp */
218
	ld8 r29 = [r31], +8 ;;   	/* load ar.bspstore */
219
	ld8 r28 = [r31], +8 ;;   	/* load ar.bspstore_new */
220
	sub r27 = r30 , r28 ;;		/* calculate loadrs (step 2) */
470 jermar 221
	shl r27 = r27, 16
222
 
223
	mov r24 = ar.rsc ;;
224
	and r30 = ~3, r24 ;;
225
	or  r24 = r30 , r27 ;;     
226
	mov ar.rsc = r24 ;;		/* place RSE in enforced lazy mode */
227
 
228
	loadrs 				/* (step 3) */
229
 
230
	ld8 r27 = [r31], +8 ;;		/* load ar.rnat */
231
	ld8 r26 = [r31], +8 ;;		/* load cr.ifs */
232
	ld8 r25 = [r31], +8 ;;		/* load ar.pfs */
233
	ld8 r24 = [r31], +8 ;;		/* load ar.rsc */
234
 
915 jermar 235
	mov ar.bspstore = r29 ;;	/* (step 4) */
236
	mov ar.rnat = r27		/* (step 5) */
470 jermar 237
 
238
	mov ar.pfs = r25		/* (step 6) */
239
	mov cr.ifs = r26	
240
 
241
	mov ar.rsc = r24		/* (step 7) */
242
 
243
    /* 17. restore interruption state from memory stack */
916 jermar 244
	ld8 r28 = [r31], +8 ;;		/* load cr.ifa */		
245
	ld8 r27 = [r31], +8 ;;		/* load cr.isr */
246
	ld8 r26 = [r31], +8 ;;		/* load cr.iipa */
247
	ld8 r25 = [r31], +8 ;;		/* load cr.ipsr */
248
	ld8 r24 = [r31], +8 ;;		/* load cr.iip */
470 jermar 249
 
1053 vana 250
	mov cr.iip = r24;;
470 jermar 251
	mov cr.iipa = r26
252
	mov cr.isr = r27
253
	mov cr.ifa = r28
1053 vana 254
			/*Set up FPU as in exception*/
255
	mov r24=psr
256
	mov r26=(PSR_DFH_MASK)
257
	mov r27=(~(PSR_DFH_MASK));;
258
	and r25=r25,r27
259
	and r24=r24,r26;;
260
	or r25=r25,r24;;
261
	mov cr.ipsr = r25
262
 
470 jermar 263
 
264
    /* 18. restore predicate registers from memory stack */
916 jermar 265
	ld8 r29 = [r31], +8 ;;		/* load predicate registers */
470 jermar 266
	mov pr = r29
267
 
268
    /* 19. return from interruption */
916 jermar 269
    	ld8 r12 = [r31]			/* load stack pointer */ 
470 jermar 270
	rfi ;;
271
 
438 jermar 272
.global heavyweight_handler_inner
273
heavyweight_handler_inner:
274
	/*
275
	 * From this point, the rest of the interrupted context
276
	 * will be preserved in stacked registers and backing store.
277
	 */
979 vana 278
	alloc loc0 = ar.pfs, 0, 48, 2, 0 ;;
438 jermar 279
 
470 jermar 280
	/* bank 0 is going to be shadowed, copy essential data from there */
911 jermar 281
	mov loc1 = R_RET	/* b0 belonging to interrupted context */
282
	mov loc2 = R_HANDLER
283
	mov out0 = R_OFFS
470 jermar 284
 
285
	add out1 = STACK_SCRATCH_AREA_SIZE, r12
438 jermar 286
 
435 jermar 287
    /* 6. switch to bank 1 and reenable PSR.ic */
478 jermar 288
	ssm PSR_IC_MASK
435 jermar 289
	bsw.1 ;;
290
	srlz.d
291
 
292
    /* 7. preserve branch and application registers */
470 jermar 293
    	mov loc3 = ar.unat
294
	mov loc4 = ar.lc
295
	mov loc5 = ar.ec
296
	mov loc6 = ar.ccv
297
	mov loc7 = ar.csd
298
	mov loc8 = ar.ssd
435 jermar 299
 
470 jermar 300
	mov loc9 = b0
301
	mov loc10 = b1
302
	mov loc11 = b2
303
	mov loc12 = b3
304
	mov loc13 = b4
305
	mov loc14 = b5
306
	mov loc15 = b6
307
	mov loc16 = b7
438 jermar 308
 
435 jermar 309
    /* 8. preserve general and floating-point registers */
310
	/* TODO: save floating-point context */
470 jermar 311
	mov loc17 = r1
312
	mov loc18 = r2
313
	mov loc19 = r3
314
	mov loc20 = r4
315
	mov loc21 = r5
316
	mov loc22 = r6
317
	mov loc23 = r7
921 jermar 318
(p5)	mov loc24 = r8		/* only if not in break_instruction handler */
470 jermar 319
	mov loc25 = r9
320
	mov loc26 = r10
321
	mov loc27 = r11
438 jermar 322
	/* skip r12 (stack pointer) */
470 jermar 323
	mov loc28 = r13
324
	mov loc29 = r14
325
	mov loc30 = r15
326
	mov loc31 = r16
327
	mov loc32 = r17
328
	mov loc33 = r18
329
	mov loc34 = r19
330
	mov loc35 = r20
331
	mov loc36 = r21
332
	mov loc37 = r22
333
	mov loc38 = r23
334
	mov loc39 = r24
335
	mov loc40 = r25
336
	mov loc41 = r26
337
	mov loc42 = r27
338
	mov loc43 = r28
339
	mov loc44 = r29
340
	mov loc45 = r30
341
	mov loc46 = r31
979 vana 342
 
1053 vana 343
	mov r24=96 + STACK_SCRATCH_AREA_SIZE
344
	mov r25=112 + STACK_SCRATCH_AREA_SIZE 
345
	mov r26=0 + STACK_SCRATCH_AREA_SIZE
346
	mov r27=16 + STACK_SCRATCH_AREA_SIZE
347
	mov r28=32 + STACK_SCRATCH_AREA_SIZE
348
	mov r29=48 + STACK_SCRATCH_AREA_SIZE
349
	mov r30=64 + STACK_SCRATCH_AREA_SIZE
350
	mov r31=80 + STACK_SCRATCH_AREA_SIZE;;
351
	add r24=r12,r24
352
	add r25=r12,r25
353
	add r26=r12,r26
354
	add r27=r12,r27
355
	add r28=r12,r28
356
	add r29=r12,r29
357
	add r30=r12,r30
358
	add r31=r12,r31;;
359
 
360
	stf.spill [r26]=f2,0x80
361
	stf.spill [r27]=f3,0x80
362
	stf.spill [r28]=f4,0x80
363
	stf.spill [r29]=f5,0x80
364
	stf.spill [r30]=f6,0x80
365
	stf.spill [r31]=f7,0x80;;
366
 
367
	stf.spill [r24]=f8,0x80
368
	stf.spill [r25]=f9,0x80
369
	stf.spill [r26]=f10,0x80
370
	stf.spill [r27]=f11,0x80
371
	stf.spill [r28]=f12,0x80
372
	stf.spill [r29]=f13,0x80
373
	stf.spill [r30]=f14,0x80
374
	stf.spill [r31]=f15,0x80;;
375
 
376
	stf.spill [r24]=f16,0x80
377
	stf.spill [r25]=f17,0x80
378
	stf.spill [r26]=f18,0x80
379
	stf.spill [r27]=f19,0x80
380
	stf.spill [r28]=f20,0x80
381
	stf.spill [r29]=f21,0x80
382
	stf.spill [r30]=f22,0x80
383
	stf.spill [r31]=f23,0x80;;
384
 
385
	stf.spill [r24]=f24,0x80
386
	stf.spill [r25]=f25,0x80
387
	stf.spill [r26]=f26,0x80
388
	stf.spill [r27]=f27,0x80
389
	stf.spill [r28]=f28,0x80
390
	stf.spill [r29]=f29,0x80
391
	stf.spill [r30]=f30,0x80
392
	stf.spill [r31]=f31,0x80;;
393
 
993 jermar 394
	/* preserve Floating point status register */
979 vana 395
	mov loc47 = ar.fpsr
438 jermar 396
 
435 jermar 397
    /* 9. skipped (will not enable interrupts) */
478 jermar 398
	/*
399
    	 * ssm PSR_I_MASK
400
	 * ;;
401
	 * srlz.d
402
	 */
238 vana 403
 
438 jermar 404
    /* 10. call handler */
919 jermar 405
    	movl r1 = _hardcoded_load_address
406
 
470 jermar 407
    	mov b1 = loc2
438 jermar 408
	br.call.sptk.many b0 = b1
409
 
410
    /* 11. return from handler */
411
0:
412
 
435 jermar 413
    /* 12. skipped (will not disable interrupts) */
478 jermar 414
	/*
415
    	 * rsm PSR_I_MASK
416
	 * ;;
417
	 * srlz.d
418
	 */
438 jermar 419
 
435 jermar 420
    /* 13. restore general and floating-point registers */
421
	/* TODO: restore floating-point context */
1053 vana 422
	mov r24=96 + STACK_SCRATCH_AREA_SIZE
423
	mov r25=112 + STACK_SCRATCH_AREA_SIZE 
424
	mov r26=0 + STACK_SCRATCH_AREA_SIZE
425
	mov r27=16 + STACK_SCRATCH_AREA_SIZE
426
	mov r28=32 + STACK_SCRATCH_AREA_SIZE
427
	mov r29=48 + STACK_SCRATCH_AREA_SIZE
428
	mov r30=64 + STACK_SCRATCH_AREA_SIZE
429
	mov r31=80 + STACK_SCRATCH_AREA_SIZE;;
430
	add r24=r12,r24
431
	add r25=r12,r25
432
	add r26=r12,r26
433
	add r27=r12,r27
434
	add r28=r12,r28
435
	add r29=r12,r29
436
	add r30=r12,r30
437
	add r31=r12,r31;;
438
 
439
 
440
	ldf.fill f2=[r26],0x80
441
	ldf.fill f3=[r27],0x80
442
	ldf.fill f4=[r28],0x80
443
	ldf.fill f5=[r29],0x80
444
	ldf.fill f6=[r30],0x80
445
	ldf.fill f7=[r31],0x80;;
446
 
447
	ldf.fill f8=[r24],0x80
448
	ldf.fill f9=[r25],0x80
449
	ldf.fill f10=[r26],0x80
450
	ldf.fill f11=[r27],0x80
451
	ldf.fill f12=[r28],0x80
452
	ldf.fill f13=[r29],0x80
453
	ldf.fill f14=[r30],0x80
454
	ldf.fill f15=[r31],0x80;;
455
 
456
	ldf.fill f16=[r24],0x80
457
	ldf.fill f17=[r25],0x80
458
	ldf.fill f18=[r26],0x80
459
	ldf.fill f19=[r27],0x80
460
	ldf.fill f20=[r28],0x80
461
	ldf.fill f21=[r29],0x80
462
	ldf.fill f22=[r30],0x80
463
	ldf.fill f23=[r31],0x80;;
464
 
465
	ldf.fill f24=[r24],0x80
466
	ldf.fill f25=[r25],0x80
467
	ldf.fill f26=[r26],0x80
468
	ldf.fill f27=[r27],0x80
469
	ldf.fill f28=[r28],0x80
470
	ldf.fill f29=[r29],0x80
471
	ldf.fill f30=[r30],0x80
472
	ldf.fill f31=[r31],0x80;;
473
 
474
 
470 jermar 475
	mov r1 = loc17
476
	mov r2 = loc18
477
	mov r3 = loc19
478
	mov r4 = loc20
479
	mov r5 = loc21
480
	mov r6 = loc22
481
	mov r7 = loc23
921 jermar 482
(p5)	mov r8 = loc24		/* only if not in break_instruction handler */
470 jermar 483
	mov r9 = loc25
484
	mov r10 = loc26
485
	mov r11 = loc27
438 jermar 486
	/* skip r12 (stack pointer) */
470 jermar 487
	mov r13 = loc28
488
	mov r14 = loc29
489
	mov r15 = loc30
490
	mov r16 = loc31
491
	mov r17 = loc32
492
	mov r18 = loc33
493
	mov r19 = loc34
494
	mov r20 = loc35
495
	mov r21 = loc36
496
	mov r22 = loc37
497
	mov r23 = loc38
498
	mov r24 = loc39
499
	mov r25 = loc40
500
	mov r26 = loc41 
501
	mov r27 = loc42
502
	mov r28 = loc43
503
	mov r29 = loc44
504
	mov r30 = loc45
505
	mov r31 = loc46
435 jermar 506
 
993 jermar 507
	/* restore Floating point status register */
979 vana 508
	mov ar.fpsr = loc47
509
 
435 jermar 510
    /* 14. restore branch and application registers */
470 jermar 511
    	mov ar.unat = loc3
512
	mov ar.lc = loc4
513
	mov ar.ec = loc5
514
	mov ar.ccv = loc6
515
	mov ar.csd = loc7
516
	mov ar.ssd = loc8
435 jermar 517
 
470 jermar 518
	mov b0 = loc9
519
	mov b1 = loc10
520
	mov b2 = loc11
521
	mov b3 = loc12
522
	mov b4 = loc13
523
	mov b5 = loc14
524
	mov b6 = loc15
525
	mov b7 = loc16
438 jermar 526
 
435 jermar 527
    /* 15. disable PSR.ic and switch to bank 0 */
478 jermar 528
	rsm PSR_IC_MASK
435 jermar 529
	bsw.0 ;;
530
	srlz.d
438 jermar 531
 
911 jermar 532
	mov R_RET = loc1
438 jermar 533
	mov ar.pfs = loc0
470 jermar 534
	br.ret.sptk.many b0
438 jermar 535
 
470 jermar 536
.global ivt
537
.align 32768
538
ivt:
539
	HEAVYWEIGHT_HANDLER 0x0000
540
	HEAVYWEIGHT_HANDLER 0x0400
541
	HEAVYWEIGHT_HANDLER 0x0800
899 jermar 542
	HEAVYWEIGHT_HANDLER 0x0c00 alternate_instruction_tlb_fault
543
	HEAVYWEIGHT_HANDLER 0x1000 alternate_data_tlb_fault
544
	HEAVYWEIGHT_HANDLER 0x1400 data_nested_tlb_fault
470 jermar 545
	HEAVYWEIGHT_HANDLER 0x1800
546
	HEAVYWEIGHT_HANDLER 0x1c00
899 jermar 547
	HEAVYWEIGHT_HANDLER 0x2000 data_dirty_bit_fault
548
	HEAVYWEIGHT_HANDLER 0x2400 instruction_access_bit_fault
549
	HEAVYWEIGHT_HANDLER 0x2800 data_access_bit_fault
470 jermar 550
	HEAVYWEIGHT_HANDLER 0x2c00 break_instruction
551
	HEAVYWEIGHT_HANDLER 0x3000 external_interrupt	/* For external interrupt, heavyweight handler is used. */
552
	HEAVYWEIGHT_HANDLER 0x3400
553
	HEAVYWEIGHT_HANDLER 0x3800
554
	HEAVYWEIGHT_HANDLER 0x3c00
555
	HEAVYWEIGHT_HANDLER 0x4000
556
	HEAVYWEIGHT_HANDLER 0x4400
557
	HEAVYWEIGHT_HANDLER 0x4800
558
	HEAVYWEIGHT_HANDLER 0x4c00
444 vana 559
 
899 jermar 560
	HEAVYWEIGHT_HANDLER 0x5000 page_not_present
470 jermar 561
	HEAVYWEIGHT_HANDLER 0x5100
562
	HEAVYWEIGHT_HANDLER 0x5200
563
	HEAVYWEIGHT_HANDLER 0x5300
564
	HEAVYWEIGHT_HANDLER 0x5400 general_exception
1023 vana 565
	HEAVYWEIGHT_HANDLER 0x5500 disabled_fp_register
470 jermar 566
	HEAVYWEIGHT_HANDLER 0x5600
567
	HEAVYWEIGHT_HANDLER 0x5700
568
	HEAVYWEIGHT_HANDLER 0x5800
569
	HEAVYWEIGHT_HANDLER 0x5900
570
	HEAVYWEIGHT_HANDLER 0x5a00
571
	HEAVYWEIGHT_HANDLER 0x5b00
572
	HEAVYWEIGHT_HANDLER 0x5c00
1023 vana 573
	HEAVYWEIGHT_HANDLER 0x5d00 
470 jermar 574
	HEAVYWEIGHT_HANDLER 0x5e00
575
	HEAVYWEIGHT_HANDLER 0x5f00
435 jermar 576
 
470 jermar 577
	HEAVYWEIGHT_HANDLER 0x6000
578
	HEAVYWEIGHT_HANDLER 0x6100
579
	HEAVYWEIGHT_HANDLER 0x6200
580
	HEAVYWEIGHT_HANDLER 0x6300
581
	HEAVYWEIGHT_HANDLER 0x6400
582
	HEAVYWEIGHT_HANDLER 0x6500
583
	HEAVYWEIGHT_HANDLER 0x6600
584
	HEAVYWEIGHT_HANDLER 0x6700
585
	HEAVYWEIGHT_HANDLER 0x6800
586
	HEAVYWEIGHT_HANDLER 0x6900
587
	HEAVYWEIGHT_HANDLER 0x6a00
588
	HEAVYWEIGHT_HANDLER 0x6b00
589
	HEAVYWEIGHT_HANDLER 0x6c00
590
	HEAVYWEIGHT_HANDLER 0x6d00
591
	HEAVYWEIGHT_HANDLER 0x6e00
592
	HEAVYWEIGHT_HANDLER 0x6f00
435 jermar 593
 
470 jermar 594
	HEAVYWEIGHT_HANDLER 0x7000
595
	HEAVYWEIGHT_HANDLER 0x7100
596
	HEAVYWEIGHT_HANDLER 0x7200
597
	HEAVYWEIGHT_HANDLER 0x7300
598
	HEAVYWEIGHT_HANDLER 0x7400
599
	HEAVYWEIGHT_HANDLER 0x7500
600
	HEAVYWEIGHT_HANDLER 0x7600
601
	HEAVYWEIGHT_HANDLER 0x7700
602
	HEAVYWEIGHT_HANDLER 0x7800
603
	HEAVYWEIGHT_HANDLER 0x7900
604
	HEAVYWEIGHT_HANDLER 0x7a00
605
	HEAVYWEIGHT_HANDLER 0x7b00
606
	HEAVYWEIGHT_HANDLER 0x7c00
607
	HEAVYWEIGHT_HANDLER 0x7d00
608
	HEAVYWEIGHT_HANDLER 0x7e00
609
	HEAVYWEIGHT_HANDLER 0x7f00
1053 vana 610
 
611
 
612
 
613