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1 jermar 1
/*
2
 * Copyright (C) 2001-2004 Jakub Jermar
3
 * All rights reserved.
4
 *
5
 * Redistribution and use in source and binary forms, with or without
6
 * modification, are permitted provided that the following conditions
7
 * are met:
8
 *
9
 * - Redistributions of source code must retain the above copyright
10
 *   notice, this list of conditions and the following disclaimer.
11
 * - Redistributions in binary form must reproduce the above copyright
12
 *   notice, this list of conditions and the following disclaimer in the
13
 *   documentation and/or other materials provided with the distribution.
14
 * - The name of the author may not be used to endorse or promote products
15
 *   derived from this software without specific prior written permission.
16
 *
17
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27
 */
28
 
1702 cejka 29
 /** @addtogroup ia32  
30
 * @{
31
 */
32
/** @file
33
 */
34
 
1 jermar 35
#include <arch/types.h>
11 jermar 36
#include <arch/smp/apic.h>
37
#include <arch/smp/ap.h>
34 jermar 38
#include <arch/smp/mps.h>
693 decky 39
#include <arch/boot/boot.h>
1 jermar 40
#include <mm/page.h>
41
#include <time/delay.h>
576 palkovsky 42
#include <interrupt.h>
1 jermar 43
#include <arch/interrupt.h>
44
#include <print.h>
45
#include <arch/asm.h>
46
#include <arch.h>
47
 
458 decky 48
#ifdef CONFIG_SMP
16 jermar 49
 
1 jermar 50
/*
512 jermar 51
 * Advanced Programmable Interrupt Controller for SMP systems.
1 jermar 52
 * Tested on:
750 jermar 53
 *  Bochs 2.0.2 - Bochs 2.2.6 with 2-8 CPUs
523 jermar 54
 *  Simics 2.0.28 - Simics 2.2.19 2-15 CPUs
516 jermar 55
 *  VMware Workstation 5.5 with 2 CPUs
812 jermar 56
 *  QEMU 0.8.0 with 2-15 CPUs
1 jermar 57
 *  ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs
437 decky 58
 *  ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs
59
 *  MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs
1 jermar 60
 */
61
 
62
/*
63
 * These variables either stay configured as initilalized, or are changed by
64
 * the MP configuration code.
65
 *
66
 * Pay special attention to the volatile keyword. Without it, gcc -O2 would
67
 * optimize the code too much and accesses to l_apic and io_apic, that must
68
 * always be 32-bit, would use byte oriented instructions.
69
 */
70
volatile __u32 *l_apic = (__u32 *) 0xfee00000;
71
volatile __u32 *io_apic = (__u32 *) 0xfec00000;
72
 
73
__u32 apic_id_mask = 0;
74
 
514 jermar 75
static int apic_poll_errors(void);
1 jermar 76
 
515 jermar 77
#ifdef LAPIC_VERBOSE
514 jermar 78
static char *delmod_str[] = {
79
    "Fixed",
80
    "Lowest Priority",
81
    "SMI",
82
    "Reserved",
83
    "NMI",
84
    "INIT",
85
    "STARTUP",
86
    "ExtInt"
87
};
88
 
89
static char *destmod_str[] = {
90
    "Physical",
91
    "Logical"
92
};
93
 
94
static char *trigmod_str[] = {
95
    "Edge",
96
    "Level"
97
};
98
 
99
static char *mask_str[] = {
100
    "Unmasked",
101
    "Masked"
102
};
103
 
104
static char *delivs_str[] = {
105
    "Idle",
106
    "Send Pending"
107
};
108
 
109
static char *tm_mode_str[] = {
110
    "One-shot",
111
    "Periodic"
112
};
113
 
114
static char *intpol_str[] = {
115
    "Polarity High",
116
    "Polarity Low"
117
};
515 jermar 118
#endif /* LAPIC_VERBOSE */
514 jermar 119
 
576 palkovsky 120
 
958 jermar 121
static void apic_spurious(int n, istate_t *istate);
122
static void l_apic_timer_interrupt(int n, istate_t *istate);
576 palkovsky 123
 
513 jermar 124
/** Initialize APIC on BSP. */
1 jermar 125
void apic_init(void)
126
{
515 jermar 127
    io_apic_id_t idreg;
128
    int i;
1 jermar 129
 
958 jermar 130
    exc_register(VECTOR_APIC_SPUR, "apic_spurious", (iroutine) apic_spurious);
1 jermar 131
 
132
    enable_irqs_function = io_apic_enable_irqs;
133
    disable_irqs_function = io_apic_disable_irqs;
134
    eoi_function = l_apic_eoi;
135
 
136
    /*
137
     * Configure interrupt routing.
138
     * IRQ 0 remains masked as the time signal is generated by l_apic's themselves.
139
     * Other interrupts will be forwarded to the lowest priority CPU.
140
     */
141
    io_apic_disable_irqs(0xffff);
958 jermar 142
    exc_register(VECTOR_CLK, "l_apic_timer", (iroutine) l_apic_timer_interrupt);
515 jermar 143
    for (i = 0; i < IRQ_COUNT; i++) {
1 jermar 144
        int pin;
145
 
512 jermar 146
        if ((pin = smp_irq_to_pin(i)) != -1) {
515 jermar 147
            io_apic_change_ioredtbl(pin, DEST_ALL, IVT_IRQBASE+i, LOPRI);
512 jermar 148
        }
1 jermar 149
    }
150
 
151
    /*
152
     * Ensure that io_apic has unique ID.
153
     */
515 jermar 154
    idreg.value = io_apic_read(IOAPICID);
155
    if ((1<<idreg.apic_id) & apic_id_mask) {    /* see if IO APIC ID is used already */
156
        for (i = 0; i < APIC_ID_COUNT; i++) {
1 jermar 157
            if (!((1<<i) & apic_id_mask)) {
515 jermar 158
                idreg.apic_id = i;
159
                io_apic_write(IOAPICID, idreg.value);
1 jermar 160
                break;
161
            }
162
        }
163
    }
164
 
165
    /*
166
     * Configure the BSP's lapic.
167
     */
168
    l_apic_init();
515 jermar 169
 
1 jermar 170
    l_apic_debug();
171
}
172
 
514 jermar 173
/** APIC spurious interrupt handler.
174
 *
175
 * @param n Interrupt vector.
1708 jermar 176
 * @param istate Interrupted state.
514 jermar 177
 */
958 jermar 178
void apic_spurious(int n, istate_t *istate)
1 jermar 179
{
1667 jermar 180
#ifdef CONFIG_DEBUG
15 jermar 181
    printf("cpu%d: APIC spurious interrupt\n", CPU->id);
1667 jermar 182
#endif
1 jermar 183
}
184
 
514 jermar 185
/** Poll for APIC errors.
186
 *
187
 * Examine Error Status Register and report all errors found.
188
 *
189
 * @return 0 on error, 1 on success.
190
 */
1 jermar 191
int apic_poll_errors(void)
192
{
514 jermar 193
    esr_t esr;
1 jermar 194
 
514 jermar 195
    esr.value = l_apic[ESR];
1 jermar 196
 
514 jermar 197
    if (esr.send_checksum_error)
515 jermar 198
        printf("Send Checksum Error\n");
514 jermar 199
    if (esr.receive_checksum_error)
515 jermar 200
        printf("Receive Checksum Error\n");
514 jermar 201
    if (esr.send_accept_error)
1 jermar 202
        printf("Send Accept Error\n");
514 jermar 203
    if (esr.receive_accept_error)
1 jermar 204
        printf("Receive Accept Error\n");
514 jermar 205
    if (esr.send_illegal_vector)
1 jermar 206
        printf("Send Illegal Vector\n");
514 jermar 207
    if (esr.received_illegal_vector)
1 jermar 208
        printf("Received Illegal Vector\n");
514 jermar 209
    if (esr.illegal_register_address)
1 jermar 210
        printf("Illegal Register Address\n");
125 jermar 211
 
514 jermar 212
    return !esr.err_bitmap;
1 jermar 213
}
214
 
514 jermar 215
/** Send all CPUs excluding CPU IPI vector.
216
 *
217
 * @param vector Interrupt vector to be sent.
218
 *
219
 * @return 0 on failure, 1 on success.
5 jermar 220
 */
221
int l_apic_broadcast_custom_ipi(__u8 vector)
222
{
513 jermar 223
    icr_t icr;
5 jermar 224
 
513 jermar 225
    icr.lo = l_apic[ICRlo];
226
    icr.delmod = DELMOD_FIXED;
227
    icr.destmod = DESTMOD_LOGIC;
228
    icr.level = LEVEL_ASSERT;
229
    icr.shorthand = SHORTHAND_ALL_EXCL;
230
    icr.trigger_mode = TRIGMOD_LEVEL;
231
    icr.vector = vector;
5 jermar 232
 
513 jermar 233
    l_apic[ICRlo] = icr.lo;
5 jermar 234
 
513 jermar 235
    icr.lo = l_apic[ICRlo];
1684 jermar 236
    if (icr.delivs == DELIVS_PENDING) {
237
#ifdef CONFIG_DEBUG
5 jermar 238
        printf("IPI is pending.\n");
1684 jermar 239
#endif
240
    }
5 jermar 241
 
242
    return apic_poll_errors();
243
}
244
 
514 jermar 245
/** Universal Start-up Algorithm for bringing up the AP processors.
246
 *
247
 * @param apicid APIC ID of the processor to be brought up.
248
 *
249
 * @return 0 on failure, 1 on success.
1 jermar 250
 */
251
int l_apic_send_init_ipi(__u8 apicid)
252
{
513 jermar 253
    icr_t icr;
1 jermar 254
    int i;
255
 
256
    /*
257
     * Read the ICR register in and zero all non-reserved fields.
258
     */
513 jermar 259
    icr.lo = l_apic[ICRlo];
260
    icr.hi = l_apic[ICRhi];
1 jermar 261
 
513 jermar 262
    icr.delmod = DELMOD_INIT;
263
    icr.destmod = DESTMOD_PHYS;
264
    icr.level = LEVEL_ASSERT;
265
    icr.trigger_mode = TRIGMOD_LEVEL;
266
    icr.shorthand = SHORTHAND_NONE;
267
    icr.vector = 0;
268
    icr.dest = apicid;
1 jermar 269
 
513 jermar 270
    l_apic[ICRhi] = icr.hi;
271
    l_apic[ICRlo] = icr.lo;
27 jermar 272
 
1 jermar 273
    /*
274
     * According to MP Specification, 20us should be enough to
275
     * deliver the IPI.
276
     */
277
    delay(20);
278
 
1684 jermar 279
    if (!apic_poll_errors())
280
        return 0;
1 jermar 281
 
513 jermar 282
    icr.lo = l_apic[ICRlo];
1684 jermar 283
    if (icr.delivs == DELIVS_PENDING) {
284
#ifdef CONFIG_DEBUG
1 jermar 285
        printf("IPI is pending.\n");
1684 jermar 286
#endif
287
    }
27 jermar 288
 
513 jermar 289
    icr.delmod = DELMOD_INIT;
290
    icr.destmod = DESTMOD_PHYS;
291
    icr.level = LEVEL_DEASSERT;
292
    icr.shorthand = SHORTHAND_NONE;
293
    icr.trigger_mode = TRIGMOD_LEVEL;
294
    icr.vector = 0;
295
    l_apic[ICRlo] = icr.lo;
1 jermar 296
 
297
    /*
298
     * Wait 10ms as MP Specification specifies.
299
     */
300
    delay(10000);
301
 
27 jermar 302
    if (!is_82489DX_apic(l_apic[LAVR])) {
303
        /*
304
         * If this is not 82489DX-based l_apic we must send two STARTUP IPI's.
305
         */
306
        for (i = 0; i<2; i++) {
513 jermar 307
            icr.lo = l_apic[ICRlo];
308
            icr.vector = ((__address) ap_boot) / 4096; /* calculate the reset vector */
309
            icr.delmod = DELMOD_STARTUP;
310
            icr.destmod = DESTMOD_PHYS;
311
            icr.level = LEVEL_ASSERT;
312
            icr.shorthand = SHORTHAND_NONE;
313
            icr.trigger_mode = TRIGMOD_LEVEL;
314
            l_apic[ICRlo] = icr.lo;
27 jermar 315
            delay(200);
316
        }
1 jermar 317
    }
318
 
319
    return apic_poll_errors();
320
}
321
 
514 jermar 322
/** Initialize Local APIC. */
1 jermar 323
void l_apic_init(void)
324
{
513 jermar 325
    lvt_error_t error;
326
    lvt_lint_t lint;
750 jermar 327
    tpr_t tpr;
513 jermar 328
    svr_t svr;
514 jermar 329
    icr_t icr;
330
    tdcr_t tdcr;
513 jermar 331
    lvt_tm_t tm;
672 jermar 332
    ldr_t ldr;
333
    dfr_t dfr;
513 jermar 334
    __u32 t1, t2;
1 jermar 335
 
513 jermar 336
    /* Initialize LVT Error register. */
337
    error.value = l_apic[LVT_Err];
338
    error.masked = true;
339
    l_apic[LVT_Err] = error.value;
1 jermar 340
 
513 jermar 341
    /* Initialize LVT LINT0 register. */
342
    lint.value = l_apic[LVT_LINT0];
343
    lint.masked = true;
344
    l_apic[LVT_LINT0] = lint.value;
1 jermar 345
 
513 jermar 346
    /* Initialize LVT LINT1 register. */
347
    lint.value = l_apic[LVT_LINT1];
348
    lint.masked = true;
349
    l_apic[LVT_LINT1] = lint.value;
750 jermar 350
 
351
    /* Task Priority Register initialization. */
352
    tpr.value = l_apic[TPR];
353
    tpr.pri_sc = 0;
354
    tpr.pri = 0;
355
    l_apic[TPR] = tpr.value;
513 jermar 356
 
357
    /* Spurious-Interrupt Vector Register initialization. */
358
    svr.value = l_apic[SVR];
359
    svr.vector = VECTOR_APIC_SPUR;
360
    svr.lapic_enabled = true;
750 jermar 361
    svr.focus_checking = true;
513 jermar 362
    l_apic[SVR] = svr.value;
363
 
31 jermar 364
    if (CPU->arch.family >= 6)
365
        enable_l_apic_in_msr();
1 jermar 366
 
513 jermar 367
    /* Interrupt Command Register initialization. */
368
    icr.lo = l_apic[ICRlo];
369
    icr.delmod = DELMOD_INIT;
370
    icr.destmod = DESTMOD_PHYS;
371
    icr.level = LEVEL_DEASSERT;
372
    icr.shorthand = SHORTHAND_ALL_INCL;
373
    icr.trigger_mode = TRIGMOD_LEVEL;
374
    l_apic[ICRlo] = icr.lo;
1 jermar 375
 
514 jermar 376
    /* Timer Divide Configuration Register initialization. */
377
    tdcr.value = l_apic[TDCR];
378
    tdcr.div_value = DIVIDE_1;
379
    l_apic[TDCR] = tdcr.value;
1 jermar 380
 
514 jermar 381
    /* Program local timer. */
513 jermar 382
    tm.value = l_apic[LVT_Tm];
383
    tm.vector = VECTOR_CLK;
384
    tm.mode = TIMER_PERIODIC;
385
    tm.masked = false;
386
    l_apic[LVT_Tm] = tm.value;
387
 
1540 jermar 388
    /*
389
     * Measure and configure the timer to generate timer
390
     * interrupt with period 1s/HZ seconds.
391
     */
1 jermar 392
    t1 = l_apic[CCRT];
393
    l_apic[ICRT] = 0xffffffff;
394
 
395
    while (l_apic[CCRT] == t1)
396
        ;
397
 
398
    t1 = l_apic[CCRT];
1540 jermar 399
    delay(1000000/HZ);
1 jermar 400
    t2 = l_apic[CCRT];
401
 
402
    l_apic[ICRT] = t1-t2;
672 jermar 403
 
404
    /* Program Logical Destination Register. */
405
    ldr.value = l_apic[LDR];
406
    if (CPU->id < sizeof(CPU->id)*8)    /* size in bits */
407
        ldr.id = (1<<CPU->id);
408
    l_apic[LDR] = ldr.value;
409
 
410
    /* Program Destination Format Register for Flat mode. */
411
    dfr.value = l_apic[DFR];
412
    dfr.model = MODEL_FLAT;
413
    l_apic[DFR] = dfr.value;
1 jermar 414
}
415
 
514 jermar 416
/** Local APIC End of Interrupt. */
1 jermar 417
void l_apic_eoi(void)
418
{
419
    l_apic[EOI] = 0;
420
}
421
 
514 jermar 422
/** Dump content of Local APIC registers. */
1 jermar 423
void l_apic_debug(void)
424
{
425
#ifdef LAPIC_VERBOSE
514 jermar 426
    lvt_tm_t tm;
427
    lvt_lint_t lint;
428
    lvt_error_t error; 
429
 
16 jermar 430
    printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id());
1 jermar 431
 
514 jermar 432
    tm.value = l_apic[LVT_Tm];
1196 cejka 433
    printf("LVT Tm: vector=%hhd, %s, %s, %s\n", tm.vector, delivs_str[tm.delivs], mask_str[tm.masked], tm_mode_str[tm.mode]);
514 jermar 434
    lint.value = l_apic[LVT_LINT0];
1196 cejka 435
    printf("LVT LINT0: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]);
514 jermar 436
    lint.value = l_apic[LVT_LINT1];
1196 cejka 437
    printf("LVT LINT1: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]); 
514 jermar 438
    error.value = l_apic[LVT_Err];
1196 cejka 439
    printf("LVT Err: vector=%hhd, %s, %s\n", error.vector, delivs_str[error.delivs], mask_str[error.masked]);
1 jermar 440
#endif
441
}
442
 
514 jermar 443
/** Local APIC Timer Interrupt.
444
 *
445
 * @param n Interrupt vector number.
1708 jermar 446
 * @param istate Interrupted state.
514 jermar 447
 */
958 jermar 448
void l_apic_timer_interrupt(int n, istate_t *istate)
1 jermar 449
{
450
    l_apic_eoi();
451
    clock();
452
}
453
 
514 jermar 454
/** Get Local APIC ID.
455
 *
456
 * @return Local APIC ID.
457
 */
81 jermar 458
__u8 l_apic_id(void)
16 jermar 459
{
515 jermar 460
    l_apic_id_t idreg;
514 jermar 461
 
515 jermar 462
    idreg.value = l_apic[L_APIC_ID];
463
    return idreg.apic_id;
16 jermar 464
}
465
 
514 jermar 466
/** Read from IO APIC register.
467
 *
468
 * @param address IO APIC register address.
469
 *
470
 * @return Content of the addressed IO APIC register.
471
 */
1 jermar 472
__u32 io_apic_read(__u8 address)
473
{
514 jermar 474
    io_regsel_t regsel;
1 jermar 475
 
514 jermar 476
    regsel.value = io_apic[IOREGSEL];
477
    regsel.reg_addr = address;
478
    io_apic[IOREGSEL] = regsel.value;
1 jermar 479
    return io_apic[IOWIN];
480
}
481
 
514 jermar 482
/** Write to IO APIC register.
483
 *
484
 * @param address IO APIC register address.
1708 jermar 485
 * @param x Content to be written to the addressed IO APIC register.
514 jermar 486
 */
1 jermar 487
void io_apic_write(__u8 address, __u32 x)
488
{
514 jermar 489
    io_regsel_t regsel;
490
 
491
    regsel.value = io_apic[IOREGSEL];
492
    regsel.reg_addr = address;
493
    io_apic[IOREGSEL] = regsel.value;
1 jermar 494
    io_apic[IOWIN] = x;
495
}
496
 
514 jermar 497
/** Change some attributes of one item in I/O Redirection Table.
498
 *
499
 * @param pin IO APIC pin number.
500
 * @param dest Interrupt destination address.
501
 * @param v Interrupt vector to trigger.
502
 * @param flags Flags.
503
 */
504
void io_apic_change_ioredtbl(int pin, int dest, __u8 v, int flags)
1 jermar 505
{
512 jermar 506
    io_redirection_reg_t reg;
514 jermar 507
    int dlvr = DELMOD_FIXED;
1 jermar 508
 
509
    if (flags & LOPRI)
512 jermar 510
        dlvr = DELMOD_LOWPRI;
511
 
514 jermar 512
    reg.lo = io_apic_read(IOREDTBL + pin*2);
513
    reg.hi = io_apic_read(IOREDTBL + pin*2 + 1);
1 jermar 514
 
672 jermar 515
    reg.dest = dest;
512 jermar 516
    reg.destmod = DESTMOD_LOGIC;
517
    reg.trigger_mode = TRIGMOD_EDGE;
518
    reg.intpol = POLARITY_HIGH;
519
    reg.delmod = dlvr;
520
    reg.intvec = v;
1 jermar 521
 
514 jermar 522
    io_apic_write(IOREDTBL + pin*2, reg.lo);
523
    io_apic_write(IOREDTBL + pin*2 + 1, reg.hi);
1 jermar 524
}
525
 
514 jermar 526
/** Mask IRQs in IO APIC.
527
 *
528
 * @param irqmask Bitmask of IRQs to be masked (0 = do not mask, 1 = mask).
529
 */
1 jermar 530
void io_apic_disable_irqs(__u16 irqmask)
531
{
512 jermar 532
    io_redirection_reg_t reg;
533
    int i, pin;
1 jermar 534
 
535
    for (i=0;i<16;i++) {
515 jermar 536
        if (irqmask & (1<<i)) {
1 jermar 537
            /*
538
             * Mask the signal input in IO APIC if there is a
539
             * mapping for the respective IRQ number.
540
             */
512 jermar 541
            pin = smp_irq_to_pin(i);
1 jermar 542
            if (pin != -1) {
512 jermar 543
                reg.lo = io_apic_read(IOREDTBL + pin*2);
544
                reg.masked = true;
545
                io_apic_write(IOREDTBL + pin*2, reg.lo);
1 jermar 546
            }
547
 
548
        }
549
    }
550
}
551
 
514 jermar 552
/** Unmask IRQs in IO APIC.
553
 *
554
 * @param irqmask Bitmask of IRQs to be unmasked (0 = do not unmask, 1 = unmask).
555
 */
1 jermar 556
void io_apic_enable_irqs(__u16 irqmask)
557
{
512 jermar 558
    int i, pin;
559
    io_redirection_reg_t reg;  
1 jermar 560
 
561
    for (i=0;i<16;i++) {
515 jermar 562
        if (irqmask & (1<<i)) {
1 jermar 563
            /*
564
             * Unmask the signal input in IO APIC if there is a
565
             * mapping for the respective IRQ number.
566
             */
512 jermar 567
            pin = smp_irq_to_pin(i);
1 jermar 568
            if (pin != -1) {
512 jermar 569
                reg.lo = io_apic_read(IOREDTBL + pin*2);
570
                reg.masked = false;
571
                io_apic_write(IOREDTBL + pin*2, reg.lo);
1 jermar 572
            }
573
 
574
        }
575
    }
576
}
577
 
458 decky 578
#endif /* CONFIG_SMP */
1702 cejka 579
 
580
 /** @}
581
 */
582