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1 jermar 1
/*
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 * Copyright (C) 2001-2004 Jakub Jermar
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 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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#include <arch/pm.h>
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#include <config.h>
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#include <arch/types.h>
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#include <typedefs.h>
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#include <arch/interrupt.h>
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#include <arch/asm.h>
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#include <arch/context.h>
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#include <panic.h>
167 jermar 37
#include <arch/mm/page.h>
814 palkovsky 38
#include <mm/slab.h>
195 vana 39
#include <memstr.h>
244 decky 40
#include <arch/boot/boot.h>
576 palkovsky 41
#include <interrupt.h>
1 jermar 42
 
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/*
11 jermar 44
 * Early ia32 configuration functions and data structures.
1 jermar 45
 */
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/*
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 * We have no use for segmentation so we set up flat mode. In this
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 * mode, we use, for each privilege level, two segments spanning the
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 * whole memory. One is for code and one is for data.
1112 palkovsky 51
 *
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 * One is for GS register which holds pointer to the TLS thread
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 * structure in it's base.
1 jermar 54
 */
1187 jermar 55
descriptor_t gdt[GDT_ITEMS] = {
125 jermar 56
    /* NULL descriptor */
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    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
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    /* KTEXT descriptor */
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    { 0xffff, 0, 0, AR_PRESENT | AR_CODE | DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 },
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    /* KDATA descriptor */
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    { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 },
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    /* UTEXT descriptor */
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    { 0xffff, 0, 0, AR_PRESENT | AR_CODE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
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    /* UDATA descriptor */
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    { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
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    /* TSS descriptor - set up will be completed later */
1112 palkovsky 67
    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1189 jermar 68
    /* TLS descriptor */
1287 vana 69
    { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
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    /* VESA Init descriptor */
1289 vana 71
    { 0xffff, 0, VESA_INIT_SEGMENT>>12, AR_PRESENT | AR_CODE | DPL_KERNEL, 0xf, 0, 0, 0, 0, 0 }
1287 vana 72
 
1 jermar 73
};
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1187 jermar 75
static idescriptor_t idt[IDT_ITEMS];
1 jermar 76
 
1187 jermar 77
static tss_t tss;
1 jermar 78
 
1187 jermar 79
tss_t *tss_p = NULL;
1 jermar 80
 
22 jermar 81
/* gdtr is changed by kmp before next CPU is initialized */
1187 jermar 82
ptr_16_32_t bootstrap_gdtr = { .limit = sizeof(gdt), .base = KA2PA((__address) gdt) };
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ptr_16_32_t gdtr = { .limit = sizeof(gdt), .base = (__address) gdt };
1 jermar 84
 
1187 jermar 85
void gdt_setbase(descriptor_t *d, __address base)
1 jermar 86
{
125 jermar 87
    d->base_0_15 = base & 0xffff;
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    d->base_16_23 = ((base) >> 16) & 0xff;
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    d->base_24_31 = ((base) >> 24) & 0xff;
1 jermar 90
}
91
 
1187 jermar 92
void gdt_setlimit(descriptor_t *d, __u32 limit)
1 jermar 93
{
125 jermar 94
    d->limit_0_15 = limit & 0xffff;
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    d->limit_16_19 = (limit >> 16) & 0xf;
1 jermar 96
}
97
 
1187 jermar 98
void idt_setoffset(idescriptor_t *d, __address offset)
1 jermar 99
{
112 jermar 100
    /*
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     * Offset is a linear address.
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     */
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    d->offset_0_15 = offset & 0xffff;
104
    d->offset_16_31 = offset >> 16;
1 jermar 105
}
106
 
1187 jermar 107
void tss_initialize(tss_t *t)
1 jermar 108
{
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    memsetb((__address) t, sizeof(struct tss), 0);
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}
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112
/*
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 * This function takes care of proper setup of IDT and IDTR.
114
 */
115
void idt_init(void)
116
{
1187 jermar 117
    idescriptor_t *d;
1 jermar 118
    int i;
125 jermar 119
 
1 jermar 120
    for (i = 0; i < IDT_ITEMS; i++) {
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        d = &idt[i];
122
 
123
        d->unused = 0;
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        d->selector = selector(KTEXT_DES);
125
 
126
        d->access = AR_PRESENT | AR_INTERRUPT;  /* masking interrupt */
127
 
128
        if (i == VECTOR_SYSCALL) {
129
            /*
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             * The syscall interrupt gate must be calleable from userland.
131
             */
132
            d->access |= DPL_USER;
133
        }
134
 
135
        idt_setoffset(d, ((__address) interrupt_handlers) + i*interrupt_handler_size);
958 jermar 136
        exc_register(i, "undef", (iroutine) null_interrupt);
1 jermar 137
    }
958 jermar 138
    exc_register(13, "gp_fault", (iroutine) gp_fault);
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    exc_register( 7, "nm_fault", (iroutine) nm_fault);
140
    exc_register(12, "ss_fault", (iroutine) ss_fault);
1019 vana 141
    exc_register(19, "simd_fp", (iroutine) simd_fp_exception);
1 jermar 142
}
143
 
144
 
144 vana 145
/* Clean IOPL(12,13) and NT(14) flags in EFLAGS register */
141 vana 146
static void clean_IOPL_NT_flags(void)
147
{
1187 jermar 148
    __asm__ volatile (
149
        "pushfl\n"
150
        "pop %%eax\n"
151
        "and $0xffff8fff, %%eax\n"
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        "push %%eax\n"
153
        "popfl\n"
154
        : : : "eax"
141 vana 155
    );
156
}
157
 
144 vana 158
/* Clean AM(18) flag in CR0 register */
143 vana 159
static void clean_AM_flag(void)
160
{
1187 jermar 161
    __asm__ volatile (
162
        "mov %%cr0, %%eax\n"
163
        "and $0xfffbffff, %%eax\n"
164
        "mov %%eax, %%cr0\n"
165
        : : : "eax"
143 vana 166
    );
167
}
141 vana 168
 
1 jermar 169
void pm_init(void)
170
{
1187 jermar 171
    descriptor_t *gdt_p = (descriptor_t *) gdtr.base;
172
    ptr_16_32_t idtr;
1 jermar 173
 
174
    /*
232 jermar 175
     * Update addresses in GDT and IDT to their virtual counterparts.
176
     */
271 decky 177
    idtr.limit = sizeof(idt);
232 jermar 178
    idtr.base = (__address) idt;
1186 jermar 179
    gdtr_load(&gdtr);
180
    idtr_load(&idtr);
232 jermar 181
 
182
    /*
1 jermar 183
     * Each CPU has its private GDT and TSS.
184
     * All CPUs share one IDT.
185
     */
186
 
187
    if (config.cpu_active == 1) {
188
        idt_init();
189
        /*
190
         * NOTE: bootstrap CPU has statically allocated TSS, because
191
         * the heap hasn't been initialized so far.
192
         */
193
        tss_p = &tss;
194
    }
195
    else {
1187 jermar 196
        tss_p = (tss_t *) malloc(sizeof(tss_t), FRAME_ATOMIC);
1 jermar 197
        if (!tss_p)
68 decky 198
            panic("could not allocate TSS\n");
1 jermar 199
    }
200
 
201
    tss_initialize(tss_p);
202
 
203
    gdt_p[TSS_DES].access = AR_PRESENT | AR_TSS | DPL_KERNEL;
204
    gdt_p[TSS_DES].special = 1;
1251 jermar 205
    gdt_p[TSS_DES].granularity = 0;
1 jermar 206
 
207
    gdt_setbase(&gdt_p[TSS_DES], (__address) tss_p);
1251 jermar 208
    gdt_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE - 1);
1 jermar 209
 
210
    /*
211
     * As of this moment, the current CPU has its own GDT pointing
212
     * to its own TSS. We just need to load the TR register.
213
     */
1186 jermar 214
    tr_load(selector(TSS_DES));
141 vana 215
 
1251 jermar 216
    clean_IOPL_NT_flags();    /* Disable I/O on nonprivileged levels and clear NT flag. */
144 vana 217
    clean_AM_flag();          /* Disable alignment check */
1 jermar 218
}
1112 palkovsky 219
 
220
void set_tls_desc(__address tls)
221
{
1187 jermar 222
    ptr_16_32_t cpugdtr;
1188 jermar 223
    descriptor_t *gdt_p;
1112 palkovsky 224
 
1186 jermar 225
    gdtr_store(&cpugdtr);
1188 jermar 226
    gdt_p = (descriptor_t *) cpugdtr.base;
1112 palkovsky 227
    gdt_setbase(&gdt_p[TLS_DES], tls);
228
    /* Reload gdt register to update GS in CPU */
1186 jermar 229
    gdtr_load(&cpugdtr);
1112 palkovsky 230
}