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| 1 | jermar | 1 | /* |
| 2 | * Copyright (C) 2001-2004 Jakub Jermar |
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| 3 | * All rights reserved. |
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| 4 | * |
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| 5 | * Redistribution and use in source and binary forms, with or without |
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| 6 | * modification, are permitted provided that the following conditions |
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| 7 | * are met: |
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| 8 | * |
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| 9 | * - Redistributions of source code must retain the above copyright |
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| 10 | * notice, this list of conditions and the following disclaimer. |
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| 11 | * - Redistributions in binary form must reproduce the above copyright |
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| 12 | * notice, this list of conditions and the following disclaimer in the |
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| 13 | * documentation and/or other materials provided with the distribution. |
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| 14 | * - The name of the author may not be used to endorse or promote products |
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| 15 | * derived from this software without specific prior written permission. |
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| 16 | * |
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 27 | */ |
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| 28 | |||
| 29 | #include <arch/pm.h> |
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| 30 | #include <config.h> |
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| 31 | #include <arch/types.h> |
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| 32 | #include <typedefs.h> |
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| 33 | #include <arch/interrupt.h> |
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| 34 | #include <arch/asm.h> |
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| 35 | #include <arch/context.h> |
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| 36 | #include <panic.h> |
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| 37 | |||
| 38 | /* |
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| 11 | jermar | 39 | * Early ia32 configuration functions and data structures. |
| 1 | jermar | 40 | */ |
| 41 | |||
| 42 | /* |
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| 43 | * We have no use for segmentation so we set up flat mode. In this |
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| 44 | * mode, we use, for each privilege level, two segments spanning the |
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| 45 | * whole memory. One is for code and one is for data. |
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| 46 | */ |
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| 47 | struct descriptor gdt[GDT_ITEMS] = { |
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| 48 | /* NULL descriptor */ |
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| 49 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, |
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| 50 | /* KTEXT descriptor */ |
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| 51 | { 0xffff, 0, 0, AR_PRESENT | AR_CODE | DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 }, |
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| 52 | /* KDATA descriptor */ |
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| 53 | { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 }, |
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| 54 | /* UTEXT descriptor */ |
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| 55 | { 0xffff, 0, 0, AR_PRESENT | AR_CODE | DPL_USER, 0xf, 0, 0, 1, 1, 0 }, |
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| 56 | /* UDATA descriptor */ |
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| 57 | { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 }, |
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| 58 | /* TSS descriptor - set up will be completed later */ |
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| 59 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } |
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| 60 | }; |
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| 61 | |||
| 62 | static struct idescriptor idt[IDT_ITEMS]; |
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| 63 | |||
| 64 | static struct tss tss; |
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| 65 | |||
| 66 | struct tss *tss_p = NULL; |
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| 67 | |||
| 22 | jermar | 68 | /* gdtr is changed by kmp before next CPU is initialized */ |
| 105 | jermar | 69 | struct ptr_16_32 gdtr __attribute__ ((section ("K_DATA_START"))) = { .limit = sizeof(gdt), .base = KA2PA((__address) gdt) }; |
| 70 | struct ptr_16_32 idtr __attribute__ ((section ("K_DATA_START"))) = { .limit = sizeof(idt), .base = KA2PA((__address) idt) }; |
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| 1 | jermar | 71 | |
| 72 | void gdt_setbase(struct descriptor *d, __address base) |
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| 73 | { |
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| 112 | jermar | 74 | d->base_0_15 = base & 0xffff; |
| 75 | d->base_16_23 = ((base) >> 16) & 0xff; |
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| 76 | d->base_24_31 = ((base) >> 24) & 0xff; |
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| 110 | jermar | 77 | |
| 1 | jermar | 78 | } |
| 79 | |||
| 105 | jermar | 80 | void gdt_setlimit(struct descriptor *d, __u32 limit) |
| 1 | jermar | 81 | { |
| 82 | d->limit_0_15 = limit & 0xffff; |
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| 83 | d->limit_16_19 = (limit >> 16) & 0xf; |
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| 84 | } |
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| 85 | |||
| 86 | void idt_setoffset(struct idescriptor *d, __address offset) |
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| 87 | { |
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| 112 | jermar | 88 | /* |
| 89 | * Offset is a linear address. |
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| 90 | */ |
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| 91 | d->offset_0_15 = offset & 0xffff; |
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| 92 | d->offset_16_31 = offset >> 16; |
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| 1 | jermar | 93 | } |
| 94 | |||
| 95 | void tss_initialize(struct tss *t) |
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| 96 | { |
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| 97 | memsetb((__address) t, sizeof(struct tss), 0); |
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| 98 | } |
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| 99 | |||
| 100 | /* |
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| 101 | * This function takes care of proper setup of IDT and IDTR. |
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| 102 | */ |
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| 103 | void idt_init(void) |
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| 104 | { |
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| 105 | struct idescriptor *d; |
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| 106 | int i; |
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| 107 | |||
| 108 | for (i = 0; i < IDT_ITEMS; i++) { |
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| 109 | d = &idt[i]; |
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| 110 | |||
| 111 | d->unused = 0; |
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| 112 | d->selector = selector(KTEXT_DES); |
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| 113 | |||
| 114 | d->access = AR_PRESENT | AR_INTERRUPT; /* masking interrupt */ |
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| 115 | |||
| 116 | if (i == VECTOR_SYSCALL) { |
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| 117 | /* |
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| 118 | * The syscall interrupt gate must be calleable from userland. |
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| 119 | */ |
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| 120 | d->access |= DPL_USER; |
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| 121 | } |
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| 122 | |||
| 123 | idt_setoffset(d, ((__address) interrupt_handlers) + i*interrupt_handler_size); |
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| 124 | trap_register(i, null_interrupt); |
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| 125 | } |
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| 126 | trap_register(13, gp_fault); |
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| 73 | vana | 127 | trap_register( 7, nm_fault); |
| 84 | vana | 128 | trap_register(12, ss_fault); |
| 1 | jermar | 129 | } |
| 130 | |||
| 131 | |||
| 132 | void pm_init(void) |
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| 133 | { |
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| 134 | struct descriptor *gdt_p = (struct descriptor *) gdtr.base; |
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| 135 | |||
| 136 | /* |
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| 137 | * Each CPU has its private GDT and TSS. |
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| 138 | * All CPUs share one IDT. |
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| 139 | */ |
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| 140 | |||
| 141 | if (config.cpu_active == 1) { |
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| 142 | idt_init(); |
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| 143 | /* |
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| 144 | * NOTE: bootstrap CPU has statically allocated TSS, because |
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| 145 | * the heap hasn't been initialized so far. |
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| 146 | */ |
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| 147 | tss_p = &tss; |
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| 148 | } |
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| 149 | else { |
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| 150 | tss_p = (struct tss *) malloc(sizeof(struct tss)); |
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| 151 | if (!tss_p) |
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| 68 | decky | 152 | panic("could not allocate TSS\n"); |
| 1 | jermar | 153 | } |
| 154 | |||
| 155 | tss_initialize(tss_p); |
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| 156 | |||
| 157 | gdt_p[TSS_DES].access = AR_PRESENT | AR_TSS | DPL_KERNEL; |
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| 158 | gdt_p[TSS_DES].special = 1; |
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| 159 | gdt_p[TSS_DES].granularity = 1; |
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| 160 | |||
| 161 | gdt_setbase(&gdt_p[TSS_DES], (__address) tss_p); |
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| 162 | gdt_setlimit(&gdt_p[TSS_DES], sizeof(struct tss) - 1); |
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| 163 | |||
| 164 | /* |
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| 165 | * As of this moment, the current CPU has its own GDT pointing |
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| 166 | * to its own TSS. We just need to load the TR register. |
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| 167 | */ |
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| 168 | __asm__("ltr %0" : : "r" ((__u16) selector(TSS_DES))); |
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| 169 | } |